3D Package Structure With Coplanar LEDs and Reduced Warpage

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Solution Overview

Problem

The increasing number of redistribution layers in three-dimensional package structures for electronic elements leads to warpage and planarity issues, which affect the performance and reliability of the package.

Innovation Solution

A package structure design with a first package and a second package, where the second package includes at least three light-emitting elements with coplanar surfaces, and the redistribution layers in the first and second packages have similar or the same number of conductive layers to balance stress and reduce warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If three-dimensional stacking structure is adopted to reduce package area, then area is reduced, but the number of redistribution layers increases causing more serious warpage

Engineering Contradiction:

Improvepackage areaVSAvoidwarpage

Core Design Contradiction:

Area of stationary objectVSShape

Solution Approach 1:

The package structure is divided into multiple sub-packages (first package, second package, third package) stacked vertically. Each sub-package contains fewer redistribution layers, which segments the overall warpage problem into manageable portions while maintaining the compact three-dimensional form factor.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different sub-packages are designed with asymmetric configurations - the first package contains a chip and first redistribution layer, the second package contains light-emitting elements and a second redistribution layer, and the third package contains a third redistribution layer. This asymmetric design allows stress distribution to be optimized across different layers, reducing overall warpage while maintaining compact area.

Inventive Principle:

Principle #4Asymmetry

2Productivity

If multiple redistribution layers are added to achieve three-dimensional stacking, then integration density is improved, but planarity deteriorates due to warpage

Engineering Contradiction:

Improveintegration densityVSAvoidplanarity

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

Each redistribution layer is designed with locally optimized properties - the first redistribution layer connects to the chip, the second redistribution layer connects to light-emitting elements, and the third redistribution layer provides external connections. This local quality optimization allows each layer to be tailored for its specific function while maintaining overall planarity through stress balancing.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By adding the vertical dimension with multiple sub-packages stacked along the thickness direction, integration density is dramatically improved while the number of redistribution layers per sub-package is reduced, thereby maintaining planarity within each layer.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If the number of redistribution layers is increased for higher integration, then device functionality is enhanced, but stress balance is disrupted causing warpage

Engineering Contradiction:

Improvedevice functionalityVSAvoidstress balance

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent employs counterbalancing stress distribution across multiple sub-packages. The first package, second package, and third package are designed with complementary stress characteristics - some layers have higher stress while others have lower stress, creating a balanced overall stress state that prevents warpage. This anti-weight approach allows enhanced device functionality through multiple redistribution layers while maintaining stress balance.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

Solution Approach 2:

The redistribution layers serve multiple functions simultaneously - they provide electrical connections between different sub-packages, act as stress management elements, and enable signal routing. This multi-functionality allows the structure to achieve high device functionality without proportionally increasing the number of redistribution layers, thereby maintaining stress balance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12469833B2Package structure and manufacturing method thereof

Publication Date: 2025.11.11 POWERTECH TECHNOLOGY INC

AI summary

A package structure and a manufacturing method thereof are provided. The package structure includes a first package and a second package, and the second package is disposed on the first package. The first package includes a first redistribution layer, at least one chip and a second redistribution layer. The chip is disposed between the first redistribution layer and the second redistribution layer. The second package includes a third redistribution layer and at least three light-emitting elements. The third redistribution layer is electrically connected to the second redistribution layer, and the second redistribution layer is disposed between the chip and the third redistribution layer. The light-emitting elements are disposed on the third redistribution layer and electrically connected to the third redistribution layer. Each light-emitting element includes a first surface opposite to the third redistribution layer, and the first surfaces of the light-emitting elements are coplanar.