Three-dimensional package architecture with face down bridge dies

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Solution Overview

Problem

Current 2.5D packaging solutions face challenges in achieving high interconnect density and efficient power delivery due to the use of solder-based technologies, which result in increased power consumption and manufacturing complexity, especially when trying to stack IC dies with pitches less than 60 micrometers in organic interposers.

Innovation Solution

A microelectronic assembly with a three-dimensional package architecture where bridge dies are positioned face down over compute dies, using interconnects with pitches less than 60 micrometers, and through-substrate vias to enable direct coupling between compute dies and the package substrate, eliminating the need for TSVs in the organic interposer and allowing for finer pitch interconnections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If solder-based technologies are used in 2.5D packaging, then interconnect density can be achieved, but power consumption increases and manufacturing complexity increases

Engineering Contradiction:
Improveinterconnect densityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent extracts the bridge die from the organic interposer and places it directly on the package substrate. This eliminates the need for solder-based interconnects through the organic interposer, thereby reducing power consumption while maintaining high interconnect density through direct coupling.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a direct coupling mechanism between the bridge die and package substrate, eliminating the organic interposer as an intermediary. This direct coupling reduces power consumption while achieving finer pitch interconnections without the limitations of solder-based technologies.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If solder-based technologies are used in 2.5D packaging, then interconnect density can be achieved, but device complexity increases

Engineering Contradiction:
Improveinterconnect densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent removes the organic interposer from the packaging architecture, extracting the complexity associated with solder-based technologies and TSV formation in organic materials. This simplifies the manufacturing process while maintaining high interconnect density through direct bridge die coupling to the package substrate.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of placing bridge dies within the organic interposer as in conventional 2.5D packaging, the patent inverts the architecture by positioning bridge dies directly on the package substrate. This inversion eliminates the need for complex solder-based interconnects through the interposer, reducing manufacturing complexity.

Inventive Principle:
Principle #13The other way round (Inversion)

3Quantity of substance

If pitches less than 60 micrometers are used to stack IC dies, then interconnect density improves, but manufacturing difficulty increases with organic interposers

Engineering Contradiction:
Improveinterconnect densityVSAvoidmanufacturing ease
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent extracts the bridge die from the organic interposer structure and places it directly on the package substrate. This eliminates the manufacturing challenges associated with forming and assembling fine-pitch TSVs in organic interposers, enabling pitches less than 60 micrometers with improved ease of manufacture.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar 2.5D architecture with bridge dies embedded in the interposer to a three-dimensional configuration where bridge dies are positioned face down directly on the package substrate. This dimensional change enables finer pitch interconnections while simplifying the manufacturing process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Reliability

If TSVs are used in organic interposers, then vertical coupling is achieved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvevertical couplingVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the TSV requirement from the organic interposer by placing bridge dies directly on the package substrate. This eliminates the need for TSVs in the organic interposer while maintaining reliable vertical coupling through the direct face-down configuration of bridge dies.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the expensive and complex TSV-based organic interposer structure with a simpler, more cost-effective direct coupling approach. The bridge dies are positioned face down directly on the package substrate, eliminating the need for costly TSV formation and assembly processes in organic materials.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS20240071933A1Three-dimensional package architecture with face down bridge dies
Publication Date: 2024.02.29 INTEL CORP
  • US20240071933A1 patent drawing
  • US20240071933A1 patent drawing
  • US20240071933A1 patent drawing

AI summary

Embodiments of a microelectronic assembly comprise: a first layer comprising a plurality of first integrated circuit (IC) dies in an organic dielectric material, the first layer having a first side and a second side opposite to the first side; a second layer on the first side of the first layer, the second layer comprising a second IC die in the organic dielectric material, the second IC die conductively coupling a pair of first IC dies in the plurality of first IC dies of the first layer; and a package substrate coupled to the second side of the first layer. The second IC die is coupled to the pair of first IC dies by interconnects having a pitch less than 60 micrometers between adjacent interconnects, and the pair of first IC dies comprises TSVs conductively coupling circuits in the first IC dies with the interconnects.