3D Package Frame Structure for Heat Dissipation and Routing

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Solution Overview

Problem

3D semiconductor packaging faces challenges in heat dissipation due to thermal hotspots and routing complexity, particularly in compact power modules with high-power devices.

Innovation Solution

A 3D package design featuring frames with supporting portions and conductive connecting portions that define assembly mounting spaces for circuit assemblies, along with an encapsulating material to enhance heat dissipation and simplify routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If 3D stacked substrate packages are used to increase circuit density, then device compactness and circuit density are improved, but heat dissipation capability deteriorates due to thermal hotspots and blocked heat paths

Engineering Contradiction:
Improvecircuit densityVSAvoidheat dissipation capability
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent segments the heat dissipation function from the electrical connection function by introducing separate heat dissipation structures (heat dissipation pads, heat dissipation layers) distinct from the electrical interconnect layers. This allows independent optimization of thermal and electrical pathways, enabling heat to be extracted from each die independently while maintaining the stacked 3D configuration for high circuit density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary thermal interface materials and heat dissipation structures between the stacked dies and the external heat sink. These intermediaries include thermally conductive encapsulant materials, heat dissipation pads, and thermal vias that facilitate heat transfer from the buried dies through the intermediate layers to the heat sink, resolving the heat dissipation bottleneck in 3D stacked packages.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Volume of moving object

If dies are stacked vertically to reduce package size, then device compactness is improved, but routing complexity increases due to difficulties in providing efficient connections between vertically arranged devices

Engineering Contradiction:
Improvepackage sizeVSAvoidrouting complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D routing to three-dimensional routing by implementing vertical vias and through-silicon vias (TSVs) that extend connections through multiple stacked layers. This dimensional change allows signals to be routed vertically between dies and horizontally within layers, providing flexible routing paths that reduce complexity compared to trying to route all connections through a single plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where multiple routing layers and interconnect structures are embedded within the stacked die configuration. Each die layer contains its own routing layer, and vertical vias nest through multiple layers to connect corresponding pads across dies, creating a hierarchical routing system that simplifies the overall connection architecture.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively addresses heat dissipation and routing challenges by providing a thermally conductive framework for efficient heat transfer and simplified electrical connections within the 3D package.

Implementation Method 1

The one or more frames each include one or more supporting portions and conductive connecting portions extending from the one or more supporting portions... providing a thermally conductive framework for efficient heat transfer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

an encapsulating material to encapsulate at least a part of the one or more frames and the circuit assemblies

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS20250125200A1Three-dimensional (3D) packages and methods for 3D packaging
Publication Date: 2025.04.17 MURATA MFG CO LTD
  • US20250125200A1 patent drawing
  • US20250125200A1 patent drawing
  • US20250125200A1 patent drawing

AI summary

A three-dimensional (3D) package includes one or more frames, circuit assemblies, and an encapsulating material to encapsulate at least a part of the one or more frames and the circuit assemblies. The one or more frames each include one or more supporting portions and conductive connecting portions extending from the one or more supporting portions and defining assembly mounting spaces therebetween. Circuit assemblies are each mounted in one assembly mounting space and electrically attached to corresponding one or more of the first and second conductive connecting portions.