3D High-Density Device Packaging for Multi-Side Heat Dissipation
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Solution Overview
Problem
Existing integrated device packages face challenges in providing adequate heat dissipation due to high device density, particularly for high-frequency and high-current draw components, leading to inefficiencies in thermal management.
Innovation Solution
A three-dimensional structure is employed in the device package, utilizing thermal interfaces on multiple sides, including a vertical substrate and energy storage devices, with passive cooling elements like inductors and heat sinks to enhance heat dissipation, and a design that maintains clearance for improved cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased to improve integration, then productivity and compactness are improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional packaging architecture. Multiple device dies are stacked vertically and connected via substrate and interconnect structures, enabling heat to be dissipated through multiple surfaces including top, bottom, and side surfaces rather than being confined to a single plane, thereby resolving the heat dissipation bottleneck caused by high device density
2Area of stationary object
If device density is increased to improve integration, then package footprint is reduced, but thermal management capability deteriorates
Solution Approach 1:
The invention employs vertical stacking of device dies and substrates to achieve high integration within a compact footprint. The three-dimensional arrangement allows heat to be conducted through multiple thermal pathways and dissipated from multiple external surfaces, maintaining effective thermal management despite the reduced package footprint
Solution Approach 2:
The patent introduces substrate structures and thermal interface materials as intermediaries between device dies and heat dissipation structures. These intermediaries facilitate efficient thermal conduction from high-density stacked devices to external heat sinks, resolving the thermal management challenge in compact packages
3Power
If high current draw components are used to improve power capability, then power output is improved, but heat generation increases
Solution Approach 1:
High current draw components are arranged in three-dimensional stacks with multiple device dies connected through vertical interconnects. This spatial distribution allows heat generated by high-power components to be conducted through multiple thermal pathways to various surfaces of the package, effectively managing heat dissipation while maintaining high power capability
4Ease of manufacture
If traditional planar packaging is used to simplify manufacturing, then ease of manufacture is improved, but heat dissipation efficiency deteriorates
Solution Approach 1:
The patent implements three-dimensional packaging using standard manufacturing techniques including sequential mounting of device dies to substrates, conventional soldering processes, and standard encapsulation methods. The vertical stacking architecture enables multi-surface heat dissipation while maintaining compatibility with existing manufacturing capabilities, achieving improved heat dissipation efficiency without sacrificing ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides efficient heat dissipation across multiple sides of the package, allowing for increased device density and higher current draw without enlarging the package footprint, effectively addressing thermal management issues.
Implementation Method 1
heat dissipation across multiple sides of the package
Implementation Method 2
passive cooling elements like inductors and heat sinks to enhance heat dissipation
Data Source
AI summary
A high-density integrated device package may include two or more primary device dies arranged along a first plane, an inductor comprising an inductor core and an inductor coil, the inductor being fixedly connected to at least one of the primary device dies, and a dielectric substrate arranged along a second plane which is substantially perpendicular to the first plane. The integrated device package further includes a secondary device die (e.g., a power IC) electrically connected to the dielectric substrate such that an orientation of the secondary device die is substantially perpendicular to that of the two or more primary device dies, wherein the dielectric substrate is fixedly connected to the inductor core, and wherein the dielectric substrate is electrically connected to at least one of the primary device dies by an edge connector.