3D Semiconductor Package Layout for Heat and Shorter Power Paths
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Solution Overview
Problem
The challenge of high temperature heat generation by semiconductor chips leading to malfunctions and the need for compact, high-integration semiconductor packages with improved electrical and structural stability.
Innovation Solution
A semiconductor package design featuring a package substrate with a power module and heat radiator, where the semiconductor chip is vertically overlapped with the power module, and connected through a connection substrate, allowing for short electrical paths and efficient thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips are mounted on multi-layered printed circuit boards with complicated designs, then multi-functionality and mass data transceiving functions are achieved, but the electronic products become larger and thicker
Solution Approach 1:
The patent implements vertical stacking of multiple functional layers including semiconductor chips, interposers, and redistribution layers within a compact three-dimensional structure. This nesting approach allows multiple functions to be integrated in the vertical direction rather than expanding horizontally, achieving multi-functionality while maintaining compact product size
Solution Approach 2:
The patent transitions from traditional planar two-dimensional circuit board layouts to a three-dimensional vertical architecture. By utilizing the vertical dimension for stacking components and routing signals through multiple layers, the design achieves higher integration density and multi-functionality without increasing the horizontal footprint of the electronic product
2Productivity
If semiconductor chips operate at high power, then mass data transceiving functions are enabled, but high temperature heat generation causes malfunctions
Solution Approach 1:
The patent extracts the heat dissipation function as a separate thermal management system independent of the electrical signal paths. Heat radiators and thermal interface materials are specifically designed to conduct heat away from the semiconductor chips through dedicated thermal pathways, allowing high-power operation while maintaining operational temperatures through active heat removal
Solution Approach 2:
The patent introduces thermal interface materials and heat radiator structures as intermediary elements between the semiconductor chips and the external environment. These intermediaries facilitate efficient heat transfer from the chip junctions through the package structure to external heat sinks, enabling high-power operation by mediating the thermal pathway without interfering with electrical functions
3Adaptability or versatility
If electrical connection paths are made longer to connect semiconductor chips to power modules, then routing flexibility is improved, but electrical properties deteriorate
Solution Approach 1:
The patent utilizes vertical vias and three-dimensional interconnect structures to route electrical signals between semiconductor chips and power modules. By transitioning from horizontal planar routing to vertical and diagonal pathways through multiple stacked layers, the design achieves both routing flexibility and short electrical path lengths, maintaining excellent electrical properties while accommodating various component layouts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances electrical properties and thermal radiation efficiency, resulting in a compact-sized semiconductor package with improved stability and reduced heat-related malfunctions.
Implementation Method 1
a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip
Implementation Method 2
the first semiconductor chip is electrically connected through the package substrate to the power module
Data Source
AI summary
A semiconductor package includes a package substrate, a power module on a first surface of the package substrate, a connector on the first surface of the package substrate, the connector being horizontally spaced apart from the power module, a first semiconductor chip on a second surface of the package substrate opposite to the first surface, and a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip. The first semiconductor chip vertically overlaps the power module, and the first semiconductor chip is electrically connected through the package substrate to the power module.