3D Semiconductor Package Layout for Heat and Power Routing
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Solution Overview
Problem
In 3D integrated circuit structures, efficient heat dissipation from the bottom semiconductor chip is hindered by the top semiconductor chip, leading to deteriorated heat dissipation characteristics and power characteristics, while also increasing manufacturing costs.
Innovation Solution
A semiconductor package configuration is proposed, comprising a first semiconductor chip with front and back side wiring structures and through vias, a second semiconductor chip disposed on the back side of the first chip with a thicker thickness, and a third semiconductor chip on the front side, where power is received through the second through via, optimizing heat dissipation and power characteristics while reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a top semiconductor chip is disposed on a bottom semiconductor chip in a 3D integrated circuit structure, then the integration density and functional capability are improved, but the heat dissipation characteristic is deteriorated
Solution Approach 1:
The patent transitions from a conventional 3D stacked architecture to a 2.5D architecture where chiplets are arranged on a substrate in a planar configuration with partial vertical stacking. This dimensional change allows heat to dissipate more effectively across the substrate while maintaining high integration density through strategic placement and interconnection of chiplets.
Solution Approach 2:
The patent divides the integrated circuit into multiple independent chiplets that can be separately manufactured, tested, and cooled. Each chiplet can be optimized for specific functions and thermal characteristics, allowing differential thermal management strategies for different functional blocks within the same package.
2Temperature
If logic chips are disposed on the top to improve heat dissipation, then the heat dissipation characteristic is improved, but the power characteristic deteriorates
Solution Approach 1:
The patent applies different functional assignments to different spatial locations within the package. High-power logic chiplets are positioned in regions with optimal thermal access to cooling structures, while I/O and memory chiplets are placed in regions optimized for their specific electrical and thermal requirements. This local optimization allows each chiplet to operate in its most efficient thermal and electrical environment.
3Power
If complex back side wiring structures are added to improve power characteristic, then the power characteristic is improved, but the manufacturing cost increases
Solution Approach 1:
The patent performs preliminary power distribution routing on the substrate before chiplet attachment. Power delivery networks are pre-configured in the substrate layer, allowing chiplets to be connected to appropriate power domains through simple bump interconnections rather than requiring complex post-attachment wiring modifications. This preliminary action simplifies the overall manufacturing process while achieving sophisticated power management.
Solution Approach 2:
The patent combines multiple functions into the substrate structure itself, including power distribution, signal routing, and thermal management pathways. By integrating these functions into the substrate rather than requiring separate wiring layers or components, the design reduces manufacturing complexity and cost while achieving the desired power characteristics.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a front side and a back side that is opposite to the front side, the first semiconductor chip includes a front side wiring structure disposed on the front side, a back side wiring structure disposed on the back side, and a first through via electrically connected to the front side wiring structure and the back side wiring structure, a second semiconductor chip disposed on the back side of the first semiconductor chip and including a second through via, and a third semiconductor chip disposed on the front side of the first semiconductor chip, wherein the first semiconductor chip receives power through the second through via, and wherein a thickness of the second semiconductor chip is greater than a thickness of the first semiconductor chip.