3D Multi-Chip Package Structure for Compact High-Density Integration
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Solution Overview
Problem
Existing package structures with multiple chips face challenges in achieving a smaller size while maintaining better quality or performance.
Innovation Solution
A package structure comprising a first chip, second and fourth chips, redistribution layers, and dielectric bodies, with conductive members connecting these components, allowing for a manufacturing method that includes forming redistribution layers and dielectric bodies to reduce thickness and improve electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple chips are integrated into a single package structure, then functionality and performance are improved, but package size increases
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional vertical stacking, where chips are arranged in multiple layers connected via through-silicon vias (TSVs). This dimensional change allows multiple functional chips to be integrated within a compact footprint, improving performance while controlling package size.
Solution Approach 2:
The patent implements nested structures where redistribution layers, dielectric materials, and conductive vias are embedded within each other in multiple stacked layers. Each layer contains functional elements that are nested within the overall package structure, maximizing space utilization and enabling high-density integration.
2Reliability
If chip integration density is increased, then performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated package into discrete functional modules (different types of chips) that can be manufactured separately and then stacked. Each chip layer can be processed independently using standard semiconductor manufacturing techniques, reducing overall manufacturing complexity despite high integration density.
Solution Approach 2:
The patent performs preliminary actions by pre-forming TSVs, redistribution layers, and dielectric structures on each chip before stacking. This preliminary preparation of interconnection structures simplifies the final assembly process and enables precise alignment, reducing manufacturing complexity for high-density integration.
Data Source
AI summary
Disclosed is a packaging structure including a first chip, a second chip, multiple fourth chips, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first dielectric body, a second dielectric body, and a conductive member. The first chip is disposed between the first redistribution layer and the third redistribution layer. The conductive member is disposed between the first redistribution layer and the second redistribution layer. The second redistribution layer is electrically connected to the first chip by the conductive member and the first redistribution layer, and is disposed between the second chip and the fourth chip. Two fourth chips are electrically connected to each other by the second redistribution layer and the second chip. The first dielectric body covers the second chip, the first redistribution layer, the second redistribution layer, and the conductive member. The second dielectric body covers the second redistribution layer.