Substrate-Free 3D Package Interconnects for Flexible Die Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces limitations in increasing circuit density due to physical constraints in two-dimensional integrated circuits, prompting the investigation of three-dimensional ICs, where bonding multiple dies or chips together with electrical connections is necessary, but existing methods are costly and less flexible due to the use of substrates and through substrate vias.
Innovation Solution
A method for manufacturing a 3D semiconductor device without a substrate, involving the formation of an interconnecting structure with multiple thin film and metal layers, where dies are bonded to this structure using under bump metallizations and connectors, and the substrate is thinned and removed, eliminating the need for through substrate vias, thus reducing costs and enhancing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional substrate-based methods with through substrate vias are used to bond multiple dies together, then electrical connections between dies can be established, but the manufacturing cost increases and flexibility decreases
Solution Approach 1:
The patent extracts and eliminates the substrate and through substrate vias from the traditional 3D IC packaging structure. Instead of forming vias through the substrate, the invention uses an interposer structure with metal layers formed on its surface to establish electrical connections between stacked dies, thereby removing the costly and inflexible substrate-based approach while maintaining reliable electrical connectivity.
2Reliability
If traditional substrate-based methods with through substrate vias are used to bond multiple dies together, then electrical connections between dies can be established, but the manufacturing flexibility decreases
Solution Approach 1:
By removing the substrate and through substrate vias, the invention enables greater manufacturing flexibility. The interposer structure with surface metal layers allows for more adaptable die stacking configurations and easier reconfiguration compared to rigid substrate-based methods, while still providing reliable electrical connections between dies.
3Productivity
If more devices are integrated into one chip in two dimensions, then circuit density improves, but the minimum feature size limit is reached and design complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of multiple dies. By stacking dies vertically and using an interposer structure with multiple metal layers to establish inter-die connections, the invention achieves higher circuit density without further reducing minimum feature size, thereby avoiding the associated increases in lithography complexity and manufacturing difficulty.
Data Source
AI summary
Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.