3D Semiconductor Package With Liquid Cooling and Shorter Interconnects
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Solution Overview
Problem
High-performance computing systems face challenges in balancing power consumption, signal integrity, and thermal management due to the complex placement of heterogeneous components on small platforms, leading to unsatisfactory thermal management and interconnection bottlenecks.
Innovation Solution
The integration of heterogeneous components using a systematic approach that includes gapless 3D integration, flexible component placement, reduced interconnection distances through die stacking, and improved thermal management with diamond or silicon wafers having embedded cooling channels, along with glass or silicon substrates with embedded decoupling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If heterogeneous components are placed on a small platform, then integration density is improved, but thermal management deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by bonding multiple circuit layers (first circuit layer, second circuit layer, third circuit layer) to each other. This dimensional change allows heterogeneous components to be distributed across multiple layers, reducing thermal density at any single location while maintaining high overall integration density.
Solution Approach 2:
The patent divides the integrated package into multiple separate circuit layers (first circuit layer with ASIC, second circuit layer with memory, third circuit layer with IO circuits) that are bonded together. This segmentation allows thermal management to be addressed at each layer level and enables better heat distribution across the three-dimensional structure.
2Area of stationary object
If heterogeneous components are placed on a small platform, then footprint is reduced, but interconnection bottlenecks worsen
Solution Approach 1:
The patent employs three-dimensional vertical stacking of circuit layers connected through through-silicon vias (TSVs) and interlayer connectors. This approach reduces interconnection distances by moving from lateral routing to vertical routing, eliminating interconnection bottlenecks while maintaining a small footprint.
Solution Approach 2:
The patent introduces an interposer structure with redistribution layers and TSVs that acts as an intermediary between different circuit layers. This interposer facilitates efficient signal and power distribution across layers, reducing interconnection complexity and bottlenecks.
3Use of energy by moving object
If power consumption is reduced, then energy efficiency is improved, but signal integrity deteriorates
Solution Approach 1:
The patent implements localized power management by providing separate power delivery networks for each circuit layer. The first circuit layer receives power through first power vias, the second circuit layer through second power vias, and the third circuit layer through third power vias. This local quality approach allows each layer to be optimized for its specific power and signal requirements, maintaining signal integrity while managing power consumption efficiently.
4Length of stationary object
If components are integrated in three-dimensional stack, then interconnection distance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary preparation of each circuit layer before stacking, including forming TSVs, redistribution layers, and bonding pads in advance. The first circuit layer is prepared with first TSVs and first redistribution layers, the second circuit layer with second TSVs and second redistribution layers, and so on. This preliminary action simplifies the final assembly process and reduces manufacturing complexity despite the three-dimensional integration.
Solution Approach 2:
The patent uses interposer structures with redistribution layers as intermediaries that simplify the bonding process between layers. These interposers provide standardized interfaces and routing, making the complex three-dimensional assembly more manageable and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves faster memory access, lower power consumption, wider bandwidth, and larger capacity while maintaining structural coherence and thermal management, enabling efficient power delivery and signal integrity in highly integrated semiconductor packages.
Implementation Method 1
The thermal layer having an embedded liquid cooling channel is bonded on the second circuit layer
Implementation Method 2
The first circuit layer is bonded to or disposed on the top surface by a first bonding (bonding interface), e.g. a die-to-wafer hybrid bonding (D2WHB)
Data Source
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AI summary
A system and a method for a semiconductor integrated package are disclosed. An interposer (210) has a top surface and a bottom surface. A first circuit layer (230) is disposed on the top surface by a first bonding and has at least one first circuit (232, 234). A second circuit layer (240) is disposed on the first circuit layer (230) by a second bonding and has at least one second circuit (242, 244). A thermal layer (260) having an embedded liquid cooling channel (265) is bonded on the second circuit layer (240).