3D Computing Package Layout for Low-Latency Logic-Memory Access
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Solution Overview
Problem
Current computing system packages face challenges in achieving high computing efficiency, bandwidth, and low latency due to complex integration of device dies with different technologies and functions, which complicates the system and increases energy consumption.
Innovation Solution
A three-tier computing system package architecture is introduced, featuring logic dies in the middle tier and memory dies in the top and bottom tiers, with bridge dies for interconnection, allowing for efficient access and scalability without increasing complexity, using semiconductor substrates and interconnect structures for bonding and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dies with different technologies and functions are integrated in the same package to achieve high computing efficiency and bandwidth, then computing efficiency and bandwidth are improved, but device complexity increases
Solution Approach 1:
The system is divided into multiple functional tiers: compute dies containing processing cores, memory dies for data storage, and I/O dies for communication. Each tier performs specialized functions, allowing complex computing tasks to be broken down into manageable segments that can be processed in parallel across multiple dies, thereby improving computing efficiency while maintaining manageable package complexity through functional specialization.
Solution Approach 2:
The patent transitions from traditional 2D side-by-side die arrangement to 3D stacking architecture where compute dies, memory dies, and I/O dies are vertically integrated across multiple layers. This dimensional change enables higher packing density and shorter inter-die communication paths, improving both computing efficiency and bandwidth without proportionally increasing package footprint complexity.
2Productivity
If more device dies are integrated in the same package to achieve high functionality packing density, then functionality packing density is improved, but device complexity increases
Solution Approach 1:
The package is segmented into standardized die types (compute dies, memory dies, I/O dies) that can be mass-produced and then systematically assembled into larger systems. This segmentation allows high functionality packing density to be achieved through modular assembly rather than custom integration, reducing system complexity by using repeatable building blocks.
Solution Approach 2:
The architecture employs universal interconnect structures and standardized bonding interfaces that can accommodate different die types and configurations. The same interconnect technology and packaging processes can be used across various system configurations, enabling high functionality packing density while reducing complexity through standardized multi-functional components.
3Loss of time
If device dies are bonded in 3D stacking manner to achieve low communication latency, then communication latency is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Interconnect structures such as through-silicon vias (TSVs) and redistribution layers are formed within each die before the bonding process. This preliminary action ensures that alignment features and electrical connections are pre-established, reducing the precision requirements during the actual bonding step and enabling 3D stacking for low latency communication.
Solution Approach 2:
The patent uses intermediary structures such as encapsulants and underfills between bonded dies to compensate for minor misalignments and stress variations. These intermediary materials act as buffers that reduce the impact of bonding precision variations, enabling 3D stacking architecture to achieve low communication latency without requiring extremely tight bonding tolerances.
Data Source
AI summary
A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.