3D Semiconductor Package Layout for Shorter Memory-Compute Links
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Solution Overview
Problem
Current semiconductor packages face challenges in enhancing reliability and durability, particularly in the stacking and connection of memory and computing dies, which affects the overall performance and yield of the semiconductor package.
Innovation Solution
A semiconductor package design featuring a buffer die, computing die, and vertically stacked memory dies with a mold layer, utilizing hybrid copper bonding and conductive pads for efficient data processing and storage, and a wafer-on-wafer structure to reduce signal distance and increase processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are vertically stacked on computing die to increase memory capacity, then memory capacity is improved, but signal distance and connection reliability deteriorate
Solution Approach 1:
A buffer die is introduced as an intermediary component between the computing die and the vertically stacked memory dies. The buffer die includes a buffer computing block that receives data from memory blocks, processes the data, and stores processed results back in memory blocks. This intermediary structure improves connection reliability by providing a dedicated processing layer that handles data transmission and processing between the computing die and multiple memory dies, reducing signal integrity issues that would arise from direct long-distance connections.
Solution Approach 2:
The computing die is divided into separate functional blocks: a computing block for data processing and a buffer computing block for data reception and temporary storage. This segmentation allows the system to handle data flow more efficiently through dedicated pathways, improving reliability by separating processing functions and reducing cross-interference in the vertical stack configuration.
2Volume of moving object
If multiple memory dies are stacked vertically to reduce package size, then package size is reduced, but manufacturing precision and alignment difficulty increase
Solution Approach 1:
The patent transitions from a traditional planar arrangement of memory and computing components to a three-dimensional vertical stack configuration. Multiple memory dies are stacked vertically above the computing die, utilizing the vertical dimension to increase memory capacity while maintaining a compact footprint. This dimensional change allows the package to achieve higher density without proportionally increasing the lateral package dimensions.
3Speed
If computing die is placed directly on buffer die to reduce signal distance, then processing speed is improved, but device complexity increases
Solution Approach 1:
The buffer computing block is merged with the buffer die structure, and the computing block is merged with the computing die. This integration creates a unified processing architecture where the computing die and buffer die work together as a coordinated system. The merging approach simplifies the overall package structure by eliminating the need for separate buffer components while maintaining the vertical stack configuration, thus improving processing speed without proportionally increasing complexity.
Data Source
AI summary
A semiconductor package include a buffer die, a computing die on the buffer die, a plurality of memory dies vertically stacked on each other to form a memory stack, wherein the memory stack is disposed on the computing die, wherein the buffer die, the computing die, and the memory stack are vertically stacked on each other, and wherein the computing die is disposed in a space between the buffer die and the memory stack, and a mold layer covering the computing die and the plurality of memory dies. The buffer die comprises a plurality of outer connection members. The computing die comprises a plurality of computing blocks. Each of the plurality of memory dies comprises a plurality of memory blocks. The plurality of computing blocks are configured to process data received from the plurality of memory blocks and to store the processed results in the plurality of memory blocks.