3D Package-on-Package Semiconductor Packaging with TAVs
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently packaging integrated circuits with increasing integration density and smaller feature sizes, requiring innovative methods to achieve denser and more compact packaging solutions while minimizing processing steps and costs.
Innovation Solution
The method involves forming a first redistribution layer (RDL) over a carrier, attaching an integrated circuit die, and then forming a second RDL, with through assembly vias (TAVs) and conductive bumps to create a streamlined 3D package-on-package structure, reducing processing steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging methods are used for integrated circuits with increasing integration density, then manufacturing simplicity is maintained, but packaging density and compactness deteriorate
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3D vertical packaging by stacking multiple integrated circuit dies vertically and connecting them through through-silicon vias (TSVs). This dimensional change enables significantly higher packaging density within the same footprint area, directly resolving the contradiction between packaging density and structural complexity.
Solution Approach 2:
The patent implements a package-on-package (PoP) architecture where multiple functional layers (memory dies, logic dies, interconnect layers) are nested vertically one above another. Each layer is precisely positioned and electrically connected to layers below, creating a compact nested structure that maximizes space utilization while maintaining organizational simplicity.
2Volume of moving object
If advanced 3D packaging techniques are implemented to achieve denser integration, then packaging compactness is improved, but processing steps and costs increase
Solution Approach 1:
The patent performs preliminary actions by pre-forming TSVs and interconnect structures on each die before final assembly. Redistribution layers (RDLs) are pre-patterned on carrier substrates to establish electrical pathways in advance. These preliminary preparations enable simpler final assembly steps and reduce the complexity of the overall manufacturing process.
Solution Approach 2:
The patent merges multiple manufacturing operations into integrated process steps. For example, TSV formation combines drilling, plating, and insulation steps; RDL formation combines deposition, patterning, and etching steps. This merging reduces the total number of discrete processing steps and simplifies the manufacturing workflow while achieving compact 3D packaging.
3Quantity of substance
If smaller feature sizes are used to increase integration density, then component integration is improved, but packaging precision requirements increase
Solution Approach 1:
The patent introduces carrier substrates and intermediary bonding layers as mediators between dies. These intermediaries provide mechanically stable platforms with precise positioning features (alignment marks, guide holes) that facilitate accurate die placement and alignment. The intermediary layers absorb and compensate for thermal expansion differences, maintaining alignment precision during manufacturing and operation.
Solution Approach 2:
The patent controls and optimizes critical parameters such as TSV diameter, wall thickness, and spacing to maintain manufacturing precision. By carefully selecting material properties (thermal expansion coefficients, mechanical strength) and dimensional parameters (via depth, RDL thickness), the patent enables high-precision alignment and bonding processes that accommodate smaller feature sizes while maintaining yield and reliability.
Data Source
AI summary
Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die.