3D Semiconductor Package Stacking With Planarized Passivation Layers
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Solution Overview
Problem
Challenges in manufacturing three-dimensional integrated circuits (3DICs) include issues related to connection failures due to uneven surface roughness and large surface recesses in the encapsulant, which affect the reliability and performance of semiconductor packages.
Innovation Solution
A method involving multiple passivation layers with planarization processes to achieve smooth surfaces, followed by the formation of redistribution layers and adhesive layers to ensure electrical and thermal connectivity, reducing surface roughness and enabling efficient thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple passivation layers with planarization processes are used to reduce surface roughness, then manufacturing precision and reliability improve, but device complexity and manufacturing time increase
Solution Approach 1:
The encapsulant is divided into multiple segments or regions with different surface characteristics. Some regions maintain original surface features while others are planarized, allowing the structure to benefit from both rough surfaces (for adhesion) and smooth surfaces (for subsequent processing) without requiring complete planarization of the entire surface.
Solution Approach 2:
Different regions of the encapsulant surface are treated differently - some areas are planarized while others retain their original roughness. This local differentiation allows the patent to achieve good adhesion in rough regions while providing smooth regions for subsequent layer deposition, reducing the need for extensive planarization processes.
2Manufacturing precision
If multiple passivation layers with planarization processes are used to reduce surface roughness, then manufacturing precision and reliability improve, but manufacturing productivity decreases
Solution Approach 1:
The encapsulant is divided into multiple segments or regions with different surface characteristics. Some regions maintain original surface features while others are planarized, allowing the structure to benefit from both rough surfaces (for adhesion) and smooth surfaces (for subsequent processing) without requiring complete planarization of the entire surface.
Solution Approach 2:
Instead of planarizing the entire encapsulant surface, the patent applies planarization only to specific regions where it is most needed. This partial action approach achieves sufficient surface quality for reliable manufacturing while significantly reducing the time and resources required compared to complete planarization.
3Strength
If the encapsulant surface is left rough to improve adhesion, then bonding strength improves, but electrical connection reliability deteriorates due to connection failures
Solution Approach 1:
The encapsulant is divided into multiple segments or regions with different surface characteristics. Some regions maintain original surface features while others are planarized, allowing the structure to benefit from both rough surfaces (for adhesion) and smooth surfaces (for subsequent processing).
Solution Approach 2:
Different regions of the encapsulant surface are treated differently - some areas are planarized while others retain their original roughness. This local differentiation allows the patent to achieve good adhesion in rough regions while providing smooth regions for subsequent layer deposition.
Solution Approach 3:
The patent introduces intermediate layers or structures between the rough encapsulant surface and the subsequent processing layers. These intermediary elements bridge the gap between the rough surface (providing adhesion) and the smooth interface needed for reliable electrical connections, allowing both requirements to be satisfied simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the reliability and performance of semiconductor packages by enhancing electrical connections, reducing connection failures, and improving thermal dissipation, thereby increasing yield and reducing package thickness.
Implementation Method 1
multiple passivation layers with planarization processes to achieve smooth surfaces
Implementation Method 2
followed by the formation of redistribution layers and adhesive layers to ensure electrical and thermal connectivity
Implementation Method 3
improving thermal dissipation
Data Source
AI summary
A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.