3D Package Layout With Embedded Passive Device for Low Loop Inductance

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Solution Overview

Problem

There is an ongoing need for smaller packages with improved performance, specifically packages with enhanced passive device performance and robust joint connections.

Innovation Solution

A package design that includes a first integrated device, an interposer, a passive device, a plurality of post interconnects, and a second integrated device, with an encapsulation layer between the first and second integrated devices, and the passive device positioned between them to improve power distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the passive device is positioned closer to the integrated device to improve power distribution, then power distribution performance is improved, but the package size may increase

Engineering Contradiction:
Improvepower distribution performanceVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The passive device is positioned in the vertical dimension between the first and second integrated devices, utilizing the z-axis space rather than lateral plane space. This allows the passive device to be closer to the integrated device for improved power distribution without increasing the package footprint, effectively resolving the contradiction between performance and size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple components are integrated in the package to improve performance, then passive device performance is improved, but the device complexity increases

Engineering Contradiction:
Improvepassive device performanceVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The package is segmented into distinct functional layers with the passive device positioned between the first and second integrated devices. This segmentation allows each component to be optimized independently while maintaining simple interconnection structures through encapsulation layers and interposers, reducing overall system complexity despite multiple high-performance components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Encapsulation layers and interposers serve as intermediary structures that simplify the integration of multiple components. These intermediaries provide standardized interfaces and routing between the passive device and integrated devices, reducing the complexity of direct connections and enabling modular assembly.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the passive device is positioned between the integrated devices to reduce loop inductance, then electrical performance is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveloop inductance reductionVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The passive device is positioned between the integrated devices during the assembly process before final encapsulation, establishing low-inductance electrical paths in advance. This preliminary positioning ensures optimal electrical performance is achieved during assembly rather than requiring complex post-fabrication adjustments or specialized manufacturing processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The positioning and interconnection of the passive device with the integrated devices are merged into a single encapsulation step. The encapsulation layer simultaneously provides structural support, electrical interconnection, and protection, reducing manufacturing complexity by combining multiple functions into one process rather than requiring separate steps for each function.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250201786A1Package comprising integrated devices and a passive device
Publication Date: 2025.06.19 QUALCOMM INC
  • US20250201786A1 patent drawing
  • US20250201786A1 patent drawing
  • US20250201786A1 patent drawing

AI summary

A package comprising a first integrated device; an interposer coupled to the first integrated device; a passive device coupled to the first integrated device; a plurality of post interconnects coupled to the first integrated device; a second integrated device coupled to the interposer, the passive device and the plurality of post interconnects; and an encapsulation layer located between the first integrated device and the second integrated device.