3D Semiconductor Package Layout for Shorter PMIC Power Paths
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Solution Overview
Problem
Conventional power management integrated circuits (PMIC) face inefficiencies due to long conductive paths and material interfaces with capacitors, leading to poor signal and power integrity, which is exacerbated by the large area occupied by passive components in electronic devices with limited space.
Innovation Solution
A semiconductor structure with 3D capacitor structures in two chips bonded by a power management die, connected through interconnects along the thickness of the structure, reducing routing distances and increasing capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PMIC and capacitors are placed on the same substrate and connected through conductive traces, then the layout is simple, but the conductive paths become long and signal integrity deteriorates
Solution Approach 1:
The patent transitions from a 2D planar layout to a 3D stacked architecture. The PMIC and capacitors are placed on different substrates (first and second substrates) and connected through vertical interconnects (through-substrate vias), creating three-dimensional conductive paths. This dimensional change dramatically shortens the conductive path length while maintaining layout simplicity, directly resolving the contradiction between layout complexity and signal integrity.
2Ease of operation
If PMIC and capacitors are placed on the same substrate, then the connection is straightforward, but power integrity becomes poor due to long conductive paths
Solution Approach 1:
The invention implements a 3D stacked configuration where the PMIC on the first substrate connects to capacitors on the second substrate through vertical interconnects. This vertical connection approach maintains ease of operation through standardized bonding processes while dramatically reducing the conductive path length, thereby improving power integrity by minimizing voltage drops and power loss along the connection paths.
3Quantity of substance
If more capacitors are integrated to improve power efficiency, then the capacitance increases, but the area occupied increases
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) to increase capacitance. By placing capacitors on a separate second substrate and connecting through vertical interconnects, the design achieves higher total capacitance without increasing the planar footprint. Multiple capacitors can be stacked vertically, effectively multiplying the capacitance density (capacitance per unit area) and resolving the contradiction between capacitance quantity and device area.
Solution Approach 2:
The 3D stacked architecture allows capacitors to be nested in the vertical dimension above the PMIC substrate. The first substrate containing the PMIC serves as the base layer, while the second substrate containing capacitors is stacked above it, creating a nested hierarchical structure. This nesting approach maximizes the use of vertical space, enabling higher capacitance integration within the same footprint area.
Data Source
AI summary
The present application discloses a semiconductor package and a method for manufacturing the semiconductor package. The semiconductor package includes a first dielectric, a first redistribution layer (RDL) disposed on a first surface of the first dielectric, a first bonding layer disposed on the first RDL, a plurality of bottom dies attached to the first bonding layer, a second dielectric filling gaps between the bottom dies, a plurality of conductive pillars disposed in the second dielectric without contacting the bottom dies, a second RDL disposed on the second dielectric and the bottom dies, a second bonding layer disposed on the second RDL, a plurality of top dies attached to the second bonding layer, a third dielectric filling gaps between the top dies, and a plurality of solder bumps disposed on a second surface of the first dielectric.