3D Semiconductor Package With Post Interconnects for Low Parasitics
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Solution Overview
Problem
Existing semiconductor packaging solutions with external components face issues of high parasitic capacitance, resistance, and signal loss due to stacked arrangements requiring expensive BGA packages and complex wire bonding operations, which reduce reliability and increase noise.
Innovation Solution
The use of post interconnects extending through a dielectric material to connect external components to semiconductor device dies within a package, providing a low resistance and low parasitic path, and allowing for external components to be mounted on the package substrate, thereby reducing the need for expensive BGA packages and complex wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If stacked package solutions (PoP) are used to reduce board area, then integration density is improved, but parasitic capacitance and resistance increase, leading to signal loss and noise
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking, arranging semiconductor dies and passive components in multiple layers above the substrate. This dimensional change reduces board area occupation while maintaining signal integrity through optimized vertical interconnect design that minimizes parasitic effects.
Solution Approach 2:
The patent implements nested packaging where passive components (capacitors, resistors) are integrated within the package structure surrounding the semiconductor die. The die is mounted on the substrate, surrounded by dielectric material, with passive components positioned in the available space, creating a nested configuration that reduces board area while controlling parasitics through short interconnect paths.
2Area of moving object
If through silicon vias (TSVs) are used to form vertical interconnects, then integration density is improved, but manufacturing complexity increases due to laser drilling and deep etching operations
Solution Approach 1:
The patent extracts the complex TSV formation process by using alternative interconnect structures. Instead of drilling through-silicon vias requiring laser drilling and deep etching, the patent employs wire bonds and post-bonding interconnect methods that extend from the die surface through the dielectric material, eliminating the need for complex via formation operations while maintaining vertical integration.
Solution Approach 2:
The patent applies preliminary action by pre-attaching passive components to the substrate before die mounting, and using pre-formed wire bonds or post structures that extend through the dielectric. This preliminary preparation simplifies subsequent assembly steps and avoids the need for complex post-die-attachment via formation operations.
3Area of moving object
If BGA packages with conductive lands and balls are stacked, then integration density is improved, but cost increases due to expensive BGA packages
Solution Approach 1:
The patent replaces expensive BGA packages with simpler, more cost-effective packaging structures. Instead of using costly BGA substrates with complex land patterns and solder balls for each stacked device, the patent employs a single substrate with wire bonds and passive components, achieving similar integration density at lower cost by eliminating the need for multiple expensive BGA packages.
4Area of moving object
If complex wire bonding operations with multiple wire loop heights and lengths are used, then integration density is improved, but reliability decreases due to reduced wire bond reliability
Solution Approach 1:
The patent applies local quality by optimizing wire bond characteristics for specific local requirements. Instead of using multiple wire loop heights and lengths throughout the package, the patent employs uniform wire bond lengths and configurations tailored to the specific die and substrate geometry, ensuring consistent mechanical and electrical properties that maximize reliability while achieving the required integration density.
Data Source
AI summary
In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.