3D Package Interconnect Layout for Thermal and Power Routing
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Solution Overview
Problem
There is a need for packages with improved electrical and thermal performance while maintaining a compact size, and existing technologies face challenges in achieving this balance.
Innovation Solution
A package design incorporating a first substrate, integrated devices with through substrate vias, an interconnection device, and a second substrate, connected via solder interconnects, which enhances electrical connectivity and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple substrates and integrated devices are stacked vertically with through substrate vias, then electrical connectivity and thermal performance are improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar to three-dimensional packaging by stacking multiple substrates and integrated devices vertically. Through substrate vias enable electrical connections through the thickness of substrates, creating high-density electrical paths in the vertical dimension. This dimensional change allows improved electrical connectivity and thermal performance without increasing the package footprint.
Solution Approach 2:
The package structure implements nesting by placing integrated devices within cavities formed in substrates. The first integrated device is positioned in a first cavity, and the second integrated device is positioned in a second cavity, with interconnection devices nested between layers. This nested arrangement maximizes space utilization and enables complex interconnections within a compact volume.
2Temperature
If integrated devices are coupled through multiple solder interconnects across stacked substrates, then thermal performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by pre-forming cavities in substrates before mounting integrated devices. The first cavity and second cavity are created in advance, allowing precise positioning of integrated devices. Solder interconnects are also prepared in advance on substrate surfaces, enabling controlled thermal pathways to be established before final assembly, thereby improving thermal performance while managing manufacturing complexity.
3Reliability
If through substrate vias are used to create high-density electrical paths, then electrical performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the electrical interconnection path into multiple discrete components: through substrate vias in the first substrate, additional vias in the second substrate, and solder interconnects joining them. This segmentation allows each via and interconnect to be independently formed and aligned, reducing the cumulative precision requirements compared to a single continuous interconnection path. The segmented approach enables high-density electrical paths while managing manufacturing precision through modular fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves thermal and power distribution network performance while providing a compact form factor, with high-density electrical paths between integrated devices.
Implementation Method 1
a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects
Implementation Method 2
The design improves thermal and power distribution network performance
Implementation Method 3
the first integrated device comprises a plurality of through substrate vias
Data Source
AI summary
A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects, wherein the first integrated device comprises a plurality of through substrate vias; an interconnection device coupled to a back side of the first integrated device through a second plurality of solder interconnects; a second substrate coupled to the first substrate through at least a third plurality of solder interconnects; and a second integrated device coupled to the second substrate and the interconnection device.