3D Package Redistribution Interconnects for Short Cycle Time
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Solution Overview
Problem
Current semiconductor manufacturing processes for 3D packaging, such as package-on-package (PoP) devices, face challenges including increased cycle time, reduced control and design flexibility due to laser drilling, contamination risks, and lower yields due to defects in build-up interconnect structures, especially in dual side fan-out wafer level chip scale packages (WLCSPs).
Innovation Solution
The implementation of a method that simultaneously fabricates first and second side redistribution interconnect structures on different manufacturing lines using standardized carriers, allowing for independent processing and testing before assembly, thereby reducing cycle time and increasing yield by avoiding defective units and minimizing total thickness variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is used to form vertical interconnect structures in PoP devices, then through mold vias can be created, but cycle time increases and manufacturing throughput decreases
Solution Approach 1:
The patent divides the interconnect structure formation into separate horizontal and vertical components. Horizontal interconnects are formed using build-up layers on the wafer surface, while vertical interconnects are formed through redistribution layers (RDL) that connect stacked devices. This segmentation eliminates the need for laser drilling through the entire package thickness, reducing cycle time and improving throughput while maintaining manufacturing precision.
2Manufacturing precision
If laser drilling is used to form through mold vias, then vertical interconnections are achieved, but control and design flexibility are reduced
Solution Approach 1:
The patent employs dynamic RDL structures that can be configured in various patterns and orientations to meet different design requirements. The horizontal and vertical interconnect components can be independently designed and optimized, providing greater adaptability and control flexibility compared to fixed laser-drilled through mold vias. This allows for reconfigurable interconnect architectures that adapt to different packaging scenarios.
3Manufacturing precision
If conductive materials are used for forming through mold vias, then vertical interconnections are created, but contamination of semiconductor die occurs
Solution Approach 1:
The patent extracts the conductive material formation process from the through-mold-via creation process. Instead of forming vias through the mold compound with conductive materials that risk contaminating the die, the patent uses separate horizontal build-up layers and vertical RDL structures that are formed independently. This separation eliminates the contamination risk while achieving the same vertical interconnection function.
4Ease of manufacture
If build-up interconnect structures are formed in dual side fan-out WLCSPs, then electrical interconnection is achieved, but defects occur reducing yield
Solution Approach 1:
The patent performs preliminary testing and validation of the build-up interconnect structures before final assembly. By implementing intermediate inspection and quality control steps during the formation process, defects can be detected and corrected early, preventing yield reduction in the final product. This preliminary action ensures high reliability while maintaining ease of manufacture.
Data Source
AI summary
A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.