3D Semiconductor Package Sidewalls to Reduce Dielectric Voids
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Solution Overview
Problem
The accumulation of stress and voids in dielectric materials between semiconductor chips due to narrow inter-chip gaps and sharp edges leads to reduced thermal conductivity and mechanical instability in 3DICs.
Innovation Solution
Defining a profile for the inter-chip spacing using isotropic and anisotropic plasma etch processes to create sloped sidewalls, reducing the width of the gap along the z-axis, and using hybrid or fusion bonding to minimize stress and void formation in dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If narrow inter-chip gaps are used to increase integration density, then more chips can be integrated into a given area, but stress and voids accumulate in dielectric materials leading to reduced thermal conductivity and mechanical instability
Solution Approach 1:
The patent applies curvature by forming sloped sidewalls in the inter-chip spacing gaps instead of sharp vertical edges. The sidewalls transition from the chip surface toward the dielectric material with a controlled slope angle, eliminating stress concentration points and preventing dielectric cracking while maintaining narrow gap dimensions for high integration density
Solution Approach 2:
The patent changes the geometric parameters of the inter-chip spacing by controlling the slope angle and width profile of the gaps. By adjusting these parameters through plasma etching processes, the design optimizes both stress distribution and thermal conductivity while preserving high chip density
2Manufacturing precision
If sharp edges are present in inter-chip spacing to maintain precise chip alignment, then positioning accuracy is improved, but stress concentration occurs leading to dielectric material cracking
Solution Approach 1:
The patent replaces sharp edges with sloped sidewalls that have controlled curvature. This geometric modification eliminates stress concentration at sharp corners while maintaining precise chip positioning through the defined slope profile, preventing dielectric cracking without sacrificing alignment accuracy
3Ease of manufacture
If conventional dielectric deposition is used in narrow gaps, then manufacturing process is simple, but voids form due to stress accumulation reducing thermal conductivity
Solution Approach 1:
The sloped sidewall geometry facilitates uniform dielectric deposition by eliminating sharp corners where voids typically form. The gradual slope allows dielectric material to flow and conform evenly throughout the inter-chip spacing, ensuring complete filling and continuous thermal pathways without voids
Solution Approach 2:
By controlling the slope angle parameter of the sidewalls, the patent optimizes dielectric material flow and deposition uniformity. This parameter adjustment ensures complete gap filling while maintaining process simplicity, achieving both ease of manufacture and high thermal conductivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces dielectric cracking and voids, enhancing thermal conductivity and mechanical stability in 3DICs by minimizing stress accumulation and ensuring uniform dielectric deposition.
Implementation Method 1
Defining a profile for the inter-chip spacing using isotropic and anisotropic plasma etch processes
Implementation Method 2
using hybrid or fusion bonding to minimize stress and void formation in dielectric materials
Data Source
AI summary
A semiconductor device includes a first and second semiconductor chip having a respective first surface and a second surface opposite to each other. The semiconductor device can include a second semiconductor chip having a third surface and a fourth surface opposite to each other. The third surface of the second semiconductor chip can face the second surface of the first semiconductor chip. A first portion of a dielectric filling material can be in contact with a first sidewall of the first semiconductor chip. A second portion of a dielectric filling material can be in contact with a second sidewall of the second semiconductor chip. The first and second portions of the dielectric filling material can have a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip.