3D Semiconductor Package Sidewalls to Reduce Dielectric Cracking
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing thermal conductivity and mechanical stress in three-dimensional integrated circuits (3DICs) due to voids and stress accumulation in dielectric materials caused by narrow inter-chip gaps and sharp edges, which can lead to dielectric cracking and reduced insulation between chips.
Innovation Solution
A method is introduced to define a profile for semiconductor chips using a combination of die saw and plasma etch processes, creating a sloped inter-chip spacing with a minimum radius of about 1 nm to reduce stress and void formation, involving isotropic or anisotropic etching to control the sidewall angles and surface roughness, and using hybrid or fusion bonding to bond chips with a dielectric filling material that reduces cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If narrow inter-chip gaps are used to reduce device size, then integration density is improved, but stress accumulation and void formation in dielectric materials increase leading to dielectric cracking
Solution Approach 1:
The patent applies curvature by forming a rounded profile at the bottom corner of the inter-chip gap with a minimum radius of about 1 nm. This curved geometry eliminates sharp edges that cause stress concentration, thereby preventing dielectric cracking while maintaining narrow inter-chip gaps for high integration density.
Solution Approach 2:
The patent changes the geometric parameters of the inter-chip gap by controlling the sidewall angles through isotropic or anisotropic etching processes. By adjusting etching conditions to create specific angle profiles, the stress distribution in the dielectric material is optimized to prevent cracking.
2Ease of manufacture
If sharp edges are present at chip corners, then manufacturing simplicity is maintained, but stress concentration increases leading to dielectric cracking
Solution Approach 1:
The patent replaces sharp edges with curved profiles at the chip corners and bottom gaps. This curvature eliminates stress concentration points while the rounded profile can be achieved through controlled etching processes, maintaining manufacturing feasibility.
Solution Approach 2:
The patent performs preliminary profiling of the chip edges and inter-chip gaps before dielectric material deposition. By pre-forming the curved profiles and controlled angles, the subsequent dielectric filling process occurs without stress concentration, preventing cracking before it can occur.
3Manufacturing precision
If vertical sidewalls are used in inter-chip gaps, then manufacturing precision is simplified, but void formation increases reducing thermal conductivity
Solution Approach 1:
The patent transitions from static vertical sidewalls to dynamic angled sidewalls with specific slopes. These angled profiles facilitate better dielectric material flow and filling during the deposition process, eliminating void formation while maintaining manufacturing precision through controlled etching angles.
Solution Approach 2:
The patent changes the sidewall angle parameter from vertical (90 degrees) to specific angled profiles through controlled isotropic or anisotropic etching. This parameter change optimizes both the filling process to eliminate voids and maintains manufacturing precision through reproducible angle control.
4Strength
If dielectric filling material is deposited to fill inter-chip gaps, then mechanical fixing is improved, but cracking occurs due to stress accumulation
Solution Approach 1:
The patent performs preliminary profiling of the inter-chip gap geometry before dielectric filling. By pre-forming curved profiles and controlled angles, the stress distribution is optimized in advance, allowing the dielectric material to be deposited without causing cracking while still achieving mechanical fixing.
Solution Approach 2:
The patent changes the geometric parameters of the inter-chip gap (sidewall angles, bottom corner radius) to optimize stress distribution. These parameter changes enable the dielectric filling material to provide mechanical fixing without accumulating stress that would lead to cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dielectric cracking and stress, enhances thermal conductivity, and improves mechanical fixing of chips by minimizing voids and surface roughness, leading to more reliable and efficient thermal management in 3DICs.
Implementation Method 1
A method is introduced to define a profile for semiconductor chips using a combination of die saw and plasma etch processes
Implementation Method 2
enhances thermal conductivity, and improves mechanical fixing of chips
Data Source
AI summary
A semiconductor device includes a first and second semiconductor chip having a respective first surface and a second surface opposite to each other. The semiconductor device can include a second semiconductor chip having a third surface and a fourth surface opposite to each other. The third surface of the second semiconductor chip can face the second surface of the first semiconductor chip. A first portion of a dielectric filling material can be in contact with a first sidewall of the first semiconductor chip. A second portion of a dielectric filling material can be in contact with a second sidewall of the second semiconductor chip. The first and second portions of the dielectric filling material can have a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip.