3D Package Conductive Strip Layout for Higher Chip Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional package structures face challenges in space utilization and integration due to the occupation of space by copper sheets, limiting the number of package units and application scenarios.
Innovation Solution
A three-dimensional package structure with a conductive strip having a bent part that electrically connects a second chip to a carrier board, using a planar segment of the bent part as a mounting platform for a third chip, allowing chips to be arranged parallel to the carrier board surface, thereby optimizing space utilization and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper sheets are used to realize electrical connections between chips and pins, then electrical connection is achieved, but space utilization rate within the package body is reduced
Solution Approach 1:
The conductive strip is divided into multiple functional segments: a first end for welding to the pin, a bent part with first and second planar segments for chip mounting, and a second end for welding to the chip. This segmentation allows the conductive strip to serve multiple functions while occupying minimal space, resolving the contradiction between achieving reliable electrical connection and maintaining high space utilization rate.
Solution Approach 2:
The conductive strip is designed as a multi-functional component that simultaneously serves as an electrical connection element (welding to pin and chip) and a mechanical mounting platform (planar segments for chip placement). This multi-functionality eliminates the need for separate copper sheets and mounting structures, thereby improving space utilization while ensuring reliable electrical connection.
2Productivity
If multiple chips are vertically stacked to improve integration, then device performance is improved, but space for additional package units is reduced
Solution Approach 1:
The patent transitions from purely vertical stacking to a hybrid arrangement where chips are mounted both vertically (on the first planar segment) and horizontally (on the second planar segment extending in the second direction). This dimensional change allows multiple chips to be integrated without completely occupying the vertical space, leaving room for additional package units while maintaining high device performance.
3Area of stationary object
If conductive strip with bent part is used to mount multiple chips, then space utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process merges the electrical connection function and the mechanical mounting function into a single integrated conductive strip structure. By combining these functions into one component rather than using separate elements, the patent reduces the total number of parts and assembly steps, thereby lowering manufacturing complexity despite the bent geometry of the strip.
Data Source
AI summary
A three-dimensional package structure and a method for forming the same are provided. The three-dimensional package structure comprises: a carrier board; a first chip located on the top surface of the carrier board; a second chip located on the side of the first chip facing away from the carrier board, a conductive strip located on the carrier board, one end of the conductive strip being electrically connected to the second chip and the other end being electrically connected to the carrier board, the conductive strip comprising a bent part, the bent part comprising a first planar segment located in a first direction on the outside the second chip, the first direction being parallel to the first planar segment; and a third chip, mounted on the first planar segment.