3D Semiconductor Package With TDV Sidewalls for Thermal and PDN Routing

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving smaller, faster, and more integrated semiconductor devices due to limitations in packaging techniques, particularly in reducing thermal resistance and providing efficient power distribution in stacked semiconductor packages.

Innovation Solution

The implementation of through dielectric vias (TDVs) and direct hybrid bonding structures in a 3D IC package, which includes an interposer, semiconductor chips, and memory stacks, reduces interfacing layers and thermal resistance while providing an independent power distribution network.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional packaging techniques are used, then manufacturing simplicity is maintained, but thermal resistance increases and power distribution efficiency deteriorates

Engineering Contradiction:

Improvethermal resistanceVSAvoidpackaging structure complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent transitions from conventional 2D packaging to 3D stacked packaging with vertical through-dielectric vias. This dimensional change allows thermal and power pathways to extend through the depth of the package, reducing thermal resistance by providing direct heat escape routes and improving power distribution by creating independent vertical networks that serve multiple stacking levels.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The packaging structure is segmented into multiple functional layers including interposer, substrate, and through-dielectric via components. This segmentation allows each layer to be optimized independently for its specific function (thermal management, power distribution, mechanical support) while collectively solving the overall thermal and power distribution challenges of the 3D package.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If smaller feature sizes are used, then integration density improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improveintegration densityVSAvoidfeature size precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

An interposer is introduced as an intermediary layer between the substrate and stacked semiconductor devices. The interposer provides a platform for high-density interconnects and bonding structures, allowing fine-pitch connections to be made at the interposer level while the overall package maintains larger external dimensions. This mediator enables integration density improvement without proportionally increasing manufacturing precision requirements across the entire package.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250316624A1Semiconductor packages and methods of fabricating thereof

Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor package includes an interposer, a first semiconductor chip disposed over the interposer and having a first surface and a second surface opposite to each other, and a second semiconductor chip disposed over the first semiconductor chip and having a top surface and a bottom surface opposite to each other. The semiconductor package further includes a dielectric sidewall disposed along a side of the first semiconductor chip and over the interposer, in which at least one first via structure is disposed vertically through the dielectric sidewall of the first semiconductor chip and electrically connected to a power distribution network (PDN).