3D Semiconductor Package Through-Via Structure for Dense Die Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient interconnects in three-dimensional integrated circuits (3DICs) due to the complexity of stacking and bonding multiple dies, which affects performance and packaging efficiency.
Innovation Solution
A semiconductor package design that includes a first die and a second die bonded back-to-face with a dielectric-to-dielectric bonding, featuring through vias with step-shaped sidewalls and a dielectric encapsulation that surrounds the second die, allowing for efficient electrical connection and redistribution layers to enhance interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple dies are stacked and bonded to achieve high integration density, then integration density and bandwidth are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the bonding process into two distinct stages: first bonding the first die to the substrate, then bonding the second die to the first die. This segmentation simplifies the overall manufacturing process by breaking down the complex multi-die stacking into manageable sequential steps, reducing bonding complexity while achieving high integration density
Solution Approach 2:
The patent transitions from planar (2D) packaging to three-dimensional (3D) stacking by bonding multiple dies vertically. This dimensional change allows multiple dies to occupy the same footprint area, significantly improving integration density without increasing the package area
2Reliability
If through vias are formed with step-shaped sidewalls to improve interconnect efficiency, then electrical connection is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the first opening and first via before bonding the second die, then forming the second opening and second via after bonding. This preliminary sequencing allows each via to be formed at the appropriate stage with proper alignment, improving electrical connection reliability while managing manufacturing precision requirements through staged processing
Solution Approach 2:
The patent implements nesting by placing the second die over the first die, with the second opening and second via positioned to align with and nest over the first opening and first via. This nested arrangement ensures proper electrical interconnection between layers while simplifying the via formation process through alignment with underlying structures
3Stability of the object's composition
If dielectric encapsulation is used to surround the second die, then structural stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the dielectric encapsulation function with the existing dielectric layers already present in the structure. By integrating the encapsulation into the overall dielectric system rather than adding it as a separate complex component, structural stability is improved while minimizing increases in manufacturing complexity
Data Source
AI summary
A semiconductor package includes a first die, a plurality of second dies and a through via. The second dies are disposed over and electrically connected to the first die. The through via is disposed between the second dies and electrically connected to the first die. The through via includes a first portion having a first width and a second portion having a second width different from the first width and disposed between the first portion and the first die. The first portion includes a first seed layer and a first conductive layer, and the first seed layer is disposed aside an interface between the first portion and the second portion.