3D Die-Stacked Package Layout With Floating TIV Alignment
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Solution Overview
Problem
Integration of multiple semiconductor devices into a single package has become a challenge in the field of semiconductor manufacturing, particularly in achieving efficient and reliable 3D packaging and 3DIC devices.
Innovation Solution
The manufacturing process involves a semiconductor carrier with embedded contact vias, where dies with TSVs are placed and encapsulated with an encapsulant and TIVs. The structure is then thinned, and additional dies are stacked, with the use of bonding layers and hybrid bonding processes to integrate the dies into a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor devices are integrated into a single package using 3D packaging, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: wafer-level packaging of first dies, thinning to expose TSVs, stacking of additional dies, and final encapsulation. This segmentation allows each stage to be optimized independently, managing overall manufacturing complexity while achieving high integration density through systematic multi-die integration.
Solution Approach 2:
The patent transitions from traditional 2D planar packaging to 3D vertical stacking. Multiple dies are integrated in the vertical dimension by stacking them after thinning the carrier to expose TSVs, enabling higher integration density without proportionally increasing lateral manufacturing complexity.
2Adaptability or versatility
If the structure is thinned to expose TSVs for die stacking, then die integration capability is improved, but corrosion and electron accumulation occur
Solution Approach 1:
The thinning process is carefully controlled to expose TSVs only to the necessary extent for die stacking, preventing excessive thinning that would cause corrosion. The process includes monitoring and stopping at the precise point where TSVs are exposed but the carrier structure remains intact, countering potential harmful effects before they occur.
Solution Approach 2:
The patent introduces intermediate processing steps between thinning and die stacking, including surface treatment and protection layers, to prevent electron accumulation and corrosion during the thinning process while maintaining TSV exposure for subsequent die integration.
3Productivity
If wafer-level packaging is used for multiple dies, then productivity is improved, but integration reliability becomes challenging
Solution Approach 1:
Dies are packaged at the wafer level with preliminary alignment and bonding structures in place before stacking. Contact vias and TSVs are pre-formed and positioned, ensuring reliable electrical connections are established before the actual die stacking operation, thereby maintaining both productivity and integration reliability.
Solution Approach 2:
The patent employs advanced bonding techniques that replace traditional mechanical assembly methods with more reliable physical and chemical bonding processes at the wafer level, enhancing integration reliability while maintaining high productivity through automated wafer-scale processing.
Data Source
AI summary
A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.