3D Package Component with TIV Redistribution for Dense Die Stacking
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Solution Overview
Problem
Current 3D packaging technologies for semiconductor components face challenges in achieving high integration density and efficient bonding, leading to limitations in miniaturization and performance.
Innovation Solution
The development of a multi-layered redistribution structure with through interlayer vias and insulating layers, allowing for the stacking and bonding of semiconductor dies and device packages, along with the use of temporary carriers and conductive terminals, to enhance electrical connectivity and mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor integration density is increased to achieve miniaturization, then device size is reduced, but bonding ability between semiconductor dies and package components deteriorates
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3D stacked packaging architecture. Multiple semiconductor dies are vertically stacked and bonded to package components in the third dimension (height direction), enabling continued miniaturization of the device footprint while maintaining adequate bonding areas on each die surface.
Solution Approach 2:
The package structure is segmented into multiple discrete layers including semiconductor dies, interposers, and package substrates stacked vertically. This segmentation allows each component to be optimized independently for bonding while achieving high overall integration density through the stacked configuration.
2Area of moving object
If multiple semiconductor packages are stacked to increase integration density, then area is reduced, but manufacturing complexity increases
Solution Approach 1:
Redistribution structures are formed on semiconductor dies and package components before the stacking and bonding processes. This preliminary preparation of conductive patterns and interconnection structures simplifies the subsequent assembly process by pre-establishing electrical pathways, reducing the complexity of post-bonding manufacturing steps.
Solution Approach 2:
Interposers are introduced as intermediary components between semiconductor dies and package substrates. These interposers provide standardized bonding interfaces and redistribution of electrical connections, simplifying the integration of multiple heterogeneous packages by mediating the interconnections between different technology nodes and package types.
3Ease of manufacture
If existing package components are used for 3D stacking, then manufacturing is simplified, but electrical connectivity and mechanical support are insufficient
Solution Approach 1:
Through interlayer vias are formed penetrating through insulating layers before final assembly, and conductive terminals are pre-positioned on redistribution structures. This preliminary formation of vertical interconnection pathways ensures adequate electrical connectivity is established before bonding, addressing the insufficiency of existing package components for 3D stacked architectures.
Data Source
AI summary
A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.