3D IC Package Structure Warpage Reduction via Segmented Molding
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient and cost-effective integration of smaller electronic components due to limitations in packaging technologies, particularly in reducing warpage and improving yield and reliability in three-dimensional integrated circuit (3DIC) devices.
Innovation Solution
A method involving the formation of a package structure using a dielectric layer with redistribution layers (RDLs), through integrated fan-out vias (TIVs), and multiple molding compounds to create a robust and compact package structure, where a first molding compound embeds semiconductor devices and TIVs, and a second molding compound surrounds the first, reducing warpage and enabling precise control over package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging technologies are used for smaller electronic components, then integration density is improved, but warpage increases and yield decreases
Solution Approach 1:
The patent divides the packaging structure into multiple segments including a first molding compound, a second molding compound, and a third molding compound, each serving distinct functions. The first molding compound encapsulates the semiconductor device, the second molding compound forms an intermediate layer, and the third molding compound provides final encapsulation. This segmentation allows independent optimization of each layer to reduce warpage while maintaining integration density.
Solution Approach 2:
The patent employs composite material structures with multiple molding compounds having different material properties. The first molding compound has different thermal expansion characteristics than the second and third molding compounds, allowing compensation for thermal stress and warpage. This composite approach enables high integration density while improving yield through reduced warpage-induced defects.
2Productivity
If conventional packaging technologies are used for smaller electronic components, then integration density is improved, but warpage increases
Solution Approach 1:
The packaging structure is segmented into multiple molding compound layers, each contributing to warpage control. The first molding compound is formed at controlled thickness to minimize initial warpage, the second molding compound provides intermediate support, and the third molding compound completes the encapsulation with optimized dimensional stability. This multi-layer segmentation effectively counteracts warpage while enabling compact packaging for high integration density.
Solution Approach 2:
The patent controls the thickness parameters of each molding compound layer to optimize warpage reduction. The first molding compound has a controlled thickness range, the second molding compound provides intermediate thickness control, and the third molding compound completes the structure with precise dimensional control. By adjusting these thickness parameters, the patent achieves minimal warpage while maintaining the compact size required for high integration density.
3Productivity
If package size is reduced for smaller components, then integration density is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent segments the package formation process into multiple sequential steps with intermediate molding compounds. The first molding compound establishes the base structure, the second molding compound provides an intermediate layer for precision control, and the third molding compound completes the final package dimensions. This segmentation allows incremental precision control at each step, achieving accurate package size control even for reduced-size high-density packages.
Solution Approach 2:
The patent performs preliminary actions by forming the first and second molding compounds before final package completion. These preliminary layers establish reference dimensions and provide mechanical support that facilitates precise control during subsequent processing steps. This preliminary structuring enables better manufacturing precision in the final package size, even as overall package dimensions are reduced for higher integration density.
Data Source
AI summary
A package structure includes a semiconductor device, a first molding compound, a through-via, a first dielectric layer, a first redistribution line, and a second molding compound. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is in the first molding compound and is electrically connected to the semiconductor device. The first dielectric layer is over the semiconductor device. The first redistribution line is in the first dielectric layer and is electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer.