3D Semiconductor Package with Wireless Logic-Memory Interconnects
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Solution Overview
Problem
There is a demand for miniaturized and high-performance semiconductor packages that can efficiently integrate heterogeneous chips, such as logic and memory chips, while maintaining effective electrical connectivity and wireless communication capabilities.
Innovation Solution
A semiconductor package design that includes a package substrate with first and second wirings, a logic chip connected to the substrate, a buffer chip with through-electrodes and connection circuits, and stacked memory chips, along with conductive vertical structures and wireless communication elements for enhanced connectivity and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple heterogeneous chips are mounted together to improve functionality, then device performance and versatility are improved, but package area increases
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacking by introducing vertical interconnections through through-electrodes and conductive vertical structures. Multiple chips (logic chip, buffer chip, memory chips) are stacked in the vertical direction, allowing heterogeneous integration without increasing package footprint area.
Solution Approach 2:
The patent implements a nested chip structure where smaller chips are positioned on top of larger chips. Specifically, memory chips are stacked on the buffer chip, which itself is positioned on the logic chip, creating a nested arrangement that maximizes vertical space utilization and reduces horizontal area occupation.
2Area of stationary object
If chip stacking is implemented to reduce package area, then miniaturization is achieved, but electrical connectivity complexity increases
Solution Approach 1:
The buffer chip serves as an intermediary between the logic chip and memory chips, providing through-electrodes that facilitate vertical electrical connections. This intermediary structure simplifies the overall connectivity by creating a hierarchical connection path: logic chip → buffer chip (through-electrodes) → memory chips, reducing the complexity of direct multi-chip interconnections.
Solution Approach 2:
The patent divides the electrical connection system into separate functional segments: through-electrodes for vertical connections through the buffer chip, and conductive vertical structures for connections between the chip structure and package substrate. This segmentation allows each connection element to be optimized independently, managing overall connectivity complexity.
3Adaptability or versatility
If wireless communication elements are added to enable wireless functionality, then communication capability is improved, but device complexity increases
Solution Approach 1:
The patent combines wireless communication functionality with existing chip structures by integrating wireless communication elements into the logic chip and buffer chip. This merging approach allows wireless capability to be added without requiring separate dedicated wireless modules, thereby reducing overall device complexity while maintaining enhanced communication versatility.
Data Source
AI summary
A semiconductor package includes a package substrate including first and second wirings, a logic chip on the package substrate, electrically connected to the first wiring, and including a first wireless communication element, a chip structure on the logic chip, and including a buffer chip containing first and second through-electrodes, a first connection circuit electrically connected to the first through-electrode, and a second connection circuit electrically connected to the second through-electrode, and a plurality of memory chips stacked on the buffer chip and electrically connected to the first and second through-electrodes, a second wireless communication element within the buffer chip or between the buffer chip and the logic chip, electrically connected to the first connection circuit, and coupled to the first wireless communication element, and a plurality of conductive vertical structures between the chip structure and the package substrate and electrically connecting the second connection circuit and the second wiring.