3D Semiconductor Package Layout Without Wire Bonds or TSVs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor package manufacturing methods are inadequate in reducing thickness and cost, particularly due to the use of wire bonds and through silicon vias, which increase complexity and expense.
Innovation Solution
A semiconductor package manufacturing method that employs a three-dimensional structure without wire bonds, utilizing through silicon vias, and flip-chip bonding, where a redistribution layer connects bond pads and conductive attachment structures, reducing thickness and eliminating the need for TSVs, thereby lowering manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds and through silicon vias are used in conventional semiconductor package manufacturing, then electrical connectivity is achieved, but thickness and manufacturing cost increase
Solution Approach 1:
The patent transitions from planar wire bond connections to three-dimensional vertical connections using conductive bumps and redistribution layers. This dimensional change allows electrical connectivity to be achieved through vertical stacking rather than lateral wire bonding, thereby reducing package thickness while maintaining connectivity reliability
Solution Approach 2:
The patent extracts and eliminates the through silicon via (TSV) structure from the conventional package design. By removing TSVs and replacing them with conductive bumps and redistribution layers formed on the surface, the invention reduces manufacturing complexity and cost while achieving the same electrical connectivity function
2Reliability
If wire bonds and through silicon vias are used in conventional semiconductor package manufacturing, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple functions into integrated structures. The redistribution layer serves both as a connection medium and as a routing structure, while conductive bumps provide both mechanical support and electrical connection. This consolidation eliminates the need for separate TSV formation and wire bonding processes, reducing manufacturing complexity
Solution Approach 2:
The patent uses standard semiconductor fabrication processes (photolithography, sputtering, electroplating) to create the connection structures, copying proven manufacturing techniques rather than requiring new specialized processes. This approach maintains manufacturing reliability while simplifying the overall manufacturing complexity
3Reliability
If wire bonds and through silicon vias are used in conventional semiconductor package manufacturing, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent changes the geometric parameters of the connection structures, using small-diameter conductive bumps (5-50 micrometers) instead of thicker wire bonds. This parameter change allows for higher density connections and reduces material consumption, thereby lowering manufacturing cost while maintaining electrical connectivity reliability
Data Source
AI summary
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.