3D Semiconductor Package Conductive Layer for Z-Axis Routing
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Solution Overview
Problem
In 3D semiconductor package structures, interposers, solder balls, and pillars occupy a large surface area, hindering miniaturization and efficient use of substrate space for signal transmission.
Innovation Solution
A semiconductor package structure with a patterned conductive layer extending on both surfaces of an encapsulant and substrate, eliminating the need for interposers and solder balls, allowing for reduced package size and increased substrate surface area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers, solder balls, or pillars are used as conductive paths in a 3D package structure, then signal transmission in the Z direction is enabled, but the surface area of the substrate is occupied and the package size cannot be decreased
Solution Approach 1:
The conductive layer is formed to extend in the Z direction (height direction) rather than relying on planar interposers or solder balls on the substrate surface. By making the conductive path vertical through the encapsulant, the solution transfers the conductive function from the XY plane to the Z axis, thereby freeing up substrate surface area while maintaining signal transmission capability.
Solution Approach 2:
The invention extracts and eliminates the need for separate interposers, solder balls, or pillars by integrating the conductive function directly into the encapsulant structure through the patterned conductive layer. This removal of discrete conductive components reduces the occupied surface area on the substrate.
2Area of stationary object
If the size of interposers, solder balls, and pillars is reduced to improve substrate surface area usage, then more surface area becomes available, but controlling the size and dimension becomes increasingly challenging
Solution Approach 1:
The invention changes the dimensional parameters of the conductive structure by forming a conductive layer that extends vertically in the Z direction with controlled thickness, rather than reducing the planar dimensions of traditional conductive elements. This parameter transformation from lateral size control to vertical thickness control simplifies the manufacturing precision requirements while maximizing substrate surface area utilization.
3Volume of stationary object
If a patterned conductive layer extending on the encapsulant surfaces is used, then package size is reduced and substrate surface area is increased, but the conductive layer must be precisely patterned on lateral surfaces
Solution Approach 1:
The encapsulant is formed with angled lateral surfaces before the conductive layer is deposited. This preliminary shaping of the encapsulant creates favorable geometric conditions for subsequent conductive layer formation, allowing the conductive material to naturally conform to the angled surfaces and simplify the patterning process while achieving the desired compact package structure.
Data Source
AI summary
At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.