3D Pass Gate Memory Layout for Higher Integration Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density while maintaining effective data storage and retrieval operations.
Innovation Solution
The semiconductor memory device incorporates a pass gate with active pillars and a gate stack, where the pass gate is positioned over the gate stack in a specific direction, and the gate stack includes conductive patterns spaced apart and stacked in the same direction. This configuration enhances integration by reducing the area occupied by the pass circuit and improving on/off characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pass gate is positioned over the gate stack in a vertical configuration with conductive patterns stacked in the first direction, then the integration degree is improved and the area occupied by the pass circuit is reduced, but the manufacturing complexity increases due to the three-dimensional structure
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical structure by stacking conductive patterns (word lines, bit lines, select lines) in the first direction above the gate stack. This vertical stacking allows multiple conductive patterns to occupy the same footprint area, significantly reducing the horizontal area occupied by the pass circuit while enabling high integration density through spatial reorganization in the vertical dimension.
Solution Approach 2:
The patent implements a nested structure where multiple conductive patterns are stacked one above another in the vertical direction, with each conductive pattern containing or supporting the next. The gate stack serves as the base structure, with conductive patterns nested above it in a hierarchical arrangement, allowing efficient use of vertical space and reducing the overall device footprint.
2Quantity of substance
If conductive patterns are spaced apart and stacked in the first direction to form a three-dimensional gate stack, then the integration density increases, but the connection structure between conductive patterns and pass circuit becomes more complex
Solution Approach 1:
The patent divides the conductive patterns into distinct segments stacked in the vertical direction, with each pattern serving a specific function (word line, bit line, select line). This segmentation allows independent optimization of each conductive pattern's position and connection, facilitating modular manufacturing processes and simplifying the overall connection structure despite the three-dimensional arrangement.
Solution Approach 2:
The patent applies different spatial arrangements and connection methods to different regions of the device. The conductive patterns are positioned at specific heights above the gate stack, with localized connection structures formed at appropriate positions. This local quality approach optimizes the connection structure for each specific region, managing complexity through spatial differentiation rather than uniform design.
3Reliability
If active pillars are formed in active holes within the pass gate, then the on/off characteristics are improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent forms active holes and active pillars within the pass gate structure during the early stages of manufacturing, before completing the full three-dimensional gate stack assembly. This preliminary action allows the active pillars to be pre-positioned and configured with appropriate doping, improving on/off characteristics while simplifying subsequent manufacturing steps by having critical components ready in advance.
Solution Approach 2:
The active pillars within the pass gate are designed to serve multiple functions: they provide the channel structure for transistor operation, define the active regions for doping, and contribute to the overall mechanical support of the pass gate structure. This self-service approach reduces the need for separate manufacturing steps and components, managing complexity through multi-functionality.
Data Source
AI summary
There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a pass gate, a plurality of active pillars respectively disposed in a plurality of active holes included in the pass gate, and a gate stack, the pass gate disposed over the gate stack in a first direction.