3D Passive Components for On-Chip Voltage Regulation
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Solution Overview
Problem
Conventional two-dimensional passive component geometries in electronic systems result in high parasitic energy loss, hinder system level compaction, and fail to provide the high-speed responses needed for dynamic voltage frequency scaling due to large parasitic impedance and inefficient voltage regulation.
Innovation Solution
The development of three-dimensional passive component architectures, such as inductors and capacitors, manufactured using direct-write methodologies, which are disposed outside the chip substrate to reduce parasitic loss and enable on-chip voltage regulation and communication, utilizing pillars and conductive traces made from ferromagnetic and conductive materials with insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional passive component geometries are used, then manufacturing is simpler, but parasitic energy loss increases and system compaction is hindered
Solution Approach 1:
The patent transitions from conventional two-dimensional passive component geometries to three-dimensional architectures. The inductors utilize vertical pillars with conductive traces wrapped around them, extending in the z-direction perpendicular to the chip substrate. This dimensional change reduces parasitic energy loss by minimizing current path length and improving magnetic field coupling efficiency, while still being manufacturable through direct-write methodologies that deposit materials layer-by-layer in a controlled manner.
2Device complexity
If two-dimensional passive component geometries are used, then device complexity is lower, but system level compaction is hindered
Solution Approach 1:
By moving passive components into the third dimension with vertical pillars rising from the chip substrate, the patent achieves significantly improved system compaction. The inductors and capacitors occupy vertical space rather than horizontal plane area, allowing multiple components to be stacked or arranged in three-dimensional configurations. This reduces the overall chip footprint while the direct-write manufacturing process keeps device complexity manageable through automated material deposition.
Solution Approach 2:
The three-dimensional inductor structure incorporates nested elements where conductive traces are wrapped around vertical pillars, creating a coil configuration that utilizes internal space efficiently. The insulator material nests around the conductive traces, and the entire structure integrates with the chip substrate architecture, allowing multiple functional layers to be nested within a compact vertical envelope.
3Reliability
If off-chip voltage regulators are used, then voltage regulation is provided, but response speed is too slow for dynamic voltage frequency scaling
Solution Approach 1:
The patent merges previously separate functions by integrating passive components (inductors and capacitors) directly with the voltage regulator circuitry on the chip substrate. This integration eliminates external interconnects and reduces the distance between regulatory elements and load, enabling fast response speeds required for dynamic voltage frequency scaling while maintaining reliable voltage regulation through optimized three-dimensional component geometries with improved Q-factors and reduced parasitic effects.
4Reliability
If off-chip voltage regulators are used, then voltage regulation is provided, but operating area is excessive
Solution Approach 1:
By integrating the voltage regulator and passive components directly onto the chip substrate in a three-dimensional architecture, the patent dramatically reduces the total operating area required for voltage regulation functionality. The vertical pillars and compact coil structures occupy minimal footprint space compared to off-chip implementations, allowing the entire voltage regulation system to be contained within a small on-chip area while maintaining full regulatory capability.
Data Source
AI summary
Three-dimensional inductors may comprise a passivation layer disposed on a substrate, a three-dimensional pillar comprising a ferromagnetic material disposed on the substrate or the passivation layer, and a conductive trace wound at least partially around the pillar. Three-dimensional capacitors may comprise a passivation layer disposed on a substrate, at least two support pillars comprising a polymeric material disposed on the passivation layer or the substrate, at least two electrodes disposed between the support pillars, a dielectric disposed between the electrodes, and a metal trace. Methods of manufacturing the three-dimensional passives, such as inductors and capacitors, may comprise direct writing the components and curing them for on-chip applications.