3D PCM-NAND Bonded Memory Architecture for Faster I/O
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Solution Overview
Problem
Conventional 3D NAND memory chips face challenges with memory density, cost, and I/O speed due to large peripheral circuits occupying chip area and thermal budget limitations, leading to inefficient data transfer and high power consumption.
Innovation Solution
The integration of 3D phase-change memory (PCM) and 3D NAND memory on separate substrates with bonding interfaces for direct electrical connections, allowing high-speed data transfer and storage, and embedding PCM as a non-volatile memory buffer to enhance memory density and reduce chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If peripheral circuits are integrated on the same chip as memory arrays, then device functionality is complete, but chip area increases and memory density decreases
Solution Approach 1:
The device is divided into two separate substrates: first substrate containing memory arrays and second substrate containing peripheral circuits. This segmentation allows each substrate to be optimized independently, increasing memory density on the first substrate while maintaining complete device functionality through the bonding interface between substrates.
Solution Approach 2:
The invention transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the first substrate with memory arrays above or beside the second substrate with peripheral circuits and bonding them through vertical bonding interfaces, the design utilizes the vertical dimension to increase memory density without proportionally increasing chip area.
2Speed
If data transfer between memory arrays and peripheral circuits occurs through conventional interconnects, then device operation is simple, but I/O speed is limited and power consumption increases
Solution Approach 1:
The bonding interface is designed with localized bonding contacts that directly connect memory cell electrodes to peripheral circuit electrodes in close proximity. This local connection reduces the distance and resistance for data transfer, enabling faster I/O speed and lower power consumption compared to conventional long-range interconnects.
Solution Approach 2:
The bonding interface acts as an intermediary structure that enables direct electrical connection between the first substrate (memory arrays) and second substrate (peripheral circuits). This intermediary bonding layer with bonding contacts provides low-resistance pathways for data transfer, improving I/O performance and reducing power consumption.
3Adaptability or versatility
If thermal budget is constrained during fabrication, then existing memory processes are compatible, but integration of additional memory types becomes difficult
Solution Approach 1:
By segmenting the device into two separately fabricated substrates that are subsequently bonded, the invention allows each substrate to be manufactured using processes compatible with its specific memory type requirements. This avoids the need to constrain all fabrication processes within a single thermal budget, enabling integration of different memory types while maintaining manufacturing precision for each.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory array efficiency, reduces die size and bit cost, and achieves higher I/O speed with lower power consumption, enabling instant-on features in devices by integrating high-speed and high-density non-volatile memory in a single device.
Implementation Method 1
a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A three-dimensional memory device (300) with 3D phase-change memory includes a first semiconductor structure (302) including a peripheral circuit, an array of 3D PCM cells (318), and a first bonding layer (324) including a plurality of first bonding contacts (326); a second semiconductor structure (304) including an array of 3D NAND memory strings (338) and a second bonding layer (328) including a plurality of second bonding contacts (330); a bonding interface (306) between the first bonding layer (324) and the second bonding layer (328), wherein the first bonding contacts (326) are in contact with the second bonding contacts (330) at the bonding interface (306).