3D Power Delivery Network Structure for Uniform Semiconductor Supply
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Solution Overview
Problem
Current semiconductor devices experience power loss and uneven power supply due to the power deliver network causing IR drop, affecting performance and efficiency.
Innovation Solution
A power deliver network structure is disposed between a power deliver line and a substrate, connected to the lowest circuit layer of an interconnect structure, comprising multiple power deliver circuit layers and vias, with dummy structures and support structures to ensure uniform and lossless power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a metal wire is disposed between a redistribution layer and a semiconductor element for power delivery, then the power deliver network can transmit voltage from power source to semiconductor elements, but power loss (IR drop) and uneven power supply occur
Solution Approach 1:
The patent transitions from traditional planar power delivery to a three-dimensional stacked architecture. Power deliver circuit layers are stacked above the lowest circuit layer of the interconnect structure, with power deliver vias providing vertical connections between layers. This vertical stacking enables shorter current paths and reduced resistance, thereby decreasing power loss while maintaining power delivery capability.
Solution Approach 2:
The power deliver network is segmented into multiple circuit layers (first power deliver circuit layer, second power deliver circuit layer, etc.) connected by power deliver vias. This segmentation allows the power delivery function to be distributed across multiple layers, reducing the current density in any single layer and minimizing IR drop effects.
2Power
If a metal wire is disposed between a redistribution layer and a semiconductor element for power delivery, then the power deliver network can transmit voltage from power source to semiconductor elements, but uneven power supply occurs
Solution Approach 1:
By stacking power deliver circuit layers vertically above the lowest circuit layer and using vertical power deliver vias for connections, the patent creates a three-dimensional power delivery network. This vertical arrangement provides multiple parallel power delivery paths, ensuring uniform power distribution to semiconductor elements across different locations and reducing power supply unevenness.
Solution Approach 2:
The power deliver circuit layers are positioned at specific vertical distances from the lowest circuit layer (e.g., first distance and second distance for different layers), allowing optimized local power delivery characteristics. This spatial arrangement enables tailored power distribution to different regions of the semiconductor element based on their specific power requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Power is delivered almost uniformly and with minimal loss to the semiconductor element, enhancing performance and efficiency by optimizing the power deliver network design.
Implementation Method 1
The first power deliver network structure is disposed between the substrate in the peripheral region and the first power deliver line, and is connected to the first power deliver line and a lowest circuit layer of the interconnect structure
Data Source
AI summary
Provided is a semiconductor including a substrate, a semiconductor element disposed on the substrate, an interconnect structure, first and second power deliver lines, and first and second power deliver network (PDN) structures. The interconnect structure is disposed in the element region, above the semiconductor element, and electrically connected with the semiconductor element. The first and the second power deliver lines are disposed above the interconnect structure and electrically connected to the first and the second power supplies, respectively. The first PDN structure is disposed between the substrate and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure. The second PDN structure is disposed between the substrate and the second power deliver line, and connected to the second power deliver line and the lowest circuit layer of the interconnect structure.