3D Phase Change Memory Array with Discrete Middle Electrodes

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Solution Overview

Problem

The manufacturing cost of three-dimensional cross-point phase change memory arrays increases with the number of memory levels, and controlled etching of selector and phase change memory layers can degrade the reliability of phase change memory cells due to undercut and etch damage during patterning.

Innovation Solution

A three-dimensional phase change memory array with discrete middle electrodes is formed without separate lithographic patterning at each device level, using a method that includes forming alternating stacks of insulating and sacrificial material layers, creating pillar cavities and dielectric isolation pillars, and replacing sacrificial material with electrically conductive strips to reduce manufacturing costs and enhance device reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate lithographic patterning is performed at each device level, then manufacturing precision can be maintained, but manufacturing cost increases with the number of memory levels

Engineering Contradiction:
Improvepatterning precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by forming the complete alternating stack structure of insulating and sacrificial material layers before any patterning operations. This preliminary stacking approach allows subsequent self-aligned patterning processes to define all horizontal structures (word lines, bit lines, isolation pillars) in fewer lithographic steps, thereby maintaining patterning precision while reducing the cumulative cost impact of multiple lithography operations across stacked memory levels

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses sacrificial material layers as intermediary structures that facilitate self-aligned patterning. These sacrificial layers are deposited between the insulating layers and are selectively removed to define the horizontal conductive structures. This intermediary approach enables precise pattern transfer without requiring separate lithographic patterning at each level, thus maintaining manufacturing precision while reducing overall manufacturing cost

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If controlled etching is performed to pattern selector and phase change memory layers, then device structure can be formed, but etch damage and undercut degrade cell reliability

Engineering Contradiction:
Improvestructure formationVSAvoidcell reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the device structure into distinct functional components formed by self-aligned patterning: insulating strips, sacrificial material strips (later replaced by conductive strips), and dielectric isolation pillars. This segmentation allows each component to be defined with precise boundaries through self-aligned processes, forming the required complex device structure while minimizing the need for aggressive etching that would cause damage or undercut, thereby preserving cell reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a copying approach where the alternating stack pattern is first formed as a complete template, and then horizontal structures are defined by self-aligned patterning that copies this template geometry. This copying method ensures that the phase change memory cells and selector layers are patterned with high fidelity to the intended design, forming the necessary device structure while avoiding the etch damage and undercut that would compromise reliability

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10381559B1Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same
Publication Date: 2019.08.13 SANDISK TECHNOLOGIES LLC
  • US10381559B1 patent drawing
  • US10381559B1 patent drawing
  • US10381559B1 patent drawing

AI summary

Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.