3D Phase Change Memory Arrays with Vertical Insulating Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current phase change memory devices face challenges in achieving high density and efficient programming with minimal power consumption due to limitations in their three-dimensional architecture and material transitions.
Innovation Solution
The development of a three-dimensional phase change memory device with a vertically repeating sequence of unit layer stacks, including insulating layers, phase change memory material layers, and electrically conductive word lines, along with vertical bit lines and insulating spacers, allows for efficient programming by controlling the cooling rate of the phase change material, minimizing cell volume, and optimizing thermal insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the cell volume is minimized to achieve high density, then the storage capacity increases, but the thermal insulation becomes insufficient leading to higher power consumption
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertical stacking, where multiple PCM layers are stacked vertically along the z-axis. This dimensional change allows high-density storage without increasing lateral footprint, and the vertical arrangement enables independent thermal management of each layer through insulating barriers positioned between layers.
Solution Approach 2:
The memory device is segmented into multiple independent PCM layers separated by insulating barrier layers. Each PCM layer can be independently programmed and thermally managed. The insulating barriers segment the thermal pathways, preventing heat from propagating to adjacent layers, thus reducing cross-talk and power consumption even in high-density configurations.
2Manufacturing precision
If the cooling rate is controlled to achieve precise resistive state transitions, then the programming precision increases, but the programming time increases
Solution Approach 1:
The patent utilizes phase transitions of the PCM material between crystalline (low resistance) and amorphous (high resistance) states. By controlling the cooling rate after heating the PCM above its melting point, precise resistive state transitions are achieved: rapid quenching produces amorphous high-resistance state, while slow cooling produces crystalline low-resistance state. This phase transition mechanism enables reliable binary state storage.
Solution Approach 2:
The programming process employs periodic electrical pulses with specific waveforms and durations. The pulse width and amplitude are carefully controlled to heat the PCM to the required temperature for phase transition, followed by controlled cooling. This periodic pulsed action enables precise timing control of the phase transition process, balancing programming speed and state precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables high-density, efficient programming of phase change memory devices with reduced power consumption, allowing for precise control over the resistive states of the phase change material, enhancing data storage capabilities.
Implementation Method 1
The transition between the amorphous state and the crystalline state can be induced by controlling the rate of cooling after application of an electrical pulse that renders the phase change memory material in a first part of a programming process.
Implementation Method 2
If rapid quenching occurs, the phase change memory material can cool into an amorphous high resistivity state.
Implementation Method 3
application of an electrical pulse that renders the phase change memory material in a first part of a programming process
Implementation Method 4
optimizing thermal insulation
Data Source
AI summary
A phase change memory device containing a phase change memory material layer includes a vertically repeating sequence of unit layer stacks located over a substrate, a plurality of openings vertically extending through the vertically repeating sequence, a plurality of vertical bit lines located within a respective one of the plurality of openings, and vertical stacks of insulating spacers. Each of the unit layer stacks includes an insulating layer, at least one of the phase change memory material layer or a threshold switch material layer, and an electrically conductive word line layer. Each of the insulating spacers laterally surrounds a respective one of the plurality of vertical bit lines, and contacts a sidewall of a respective one of the electrically conductive word line layers.