3D Pixel Transistor Imaging Layout With Direct Through-Wiring
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Solution Overview
Problem
Existing three-dimensional imaging devices face challenges in improving the area efficiency of the second substrate where the readout circuit is formed, particularly in reducing the area required for components other than the pixel transistor.
Innovation Solution
The imaging device incorporates a first semiconductor layer with a photoelectric conversion section and a charge accumulation section, and a second semiconductor layer with a pixel transistor having a three-dimensional structure, where a through-wiring line directly couples the charge accumulation section and the gate electrode of the pixel transistor, reducing the area needed for components on the second semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar coupling methods are used between charge accumulation section and pixel transistor, then connection reliability is maintained, but area efficiency of the second substrate deteriorates due to larger routing area requirements
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical wiring by introducing through-wiring lines that extend in the thickness direction of the substrate. This dimensional change allows direct coupling between the charge accumulation section and pixel transistor gate electrode, significantly reducing the area required for wiring routes on the second substrate while maintaining connection reliability.
2Area of stationary object
If through-wiring line directly couples charge accumulation section and pixel transistor gate electrode, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The through-wiring line is formed by nesting multiple processing steps including insulating film deposition, patterning, and etching. The wiring line is embedded within insulating films in a nested structure, which provides mechanical support and electrical isolation, thereby reducing the impact of manufacturing variations and improving overall precision.
3Reliability
If more wiring components are added to couple charge accumulation and pixel transistor, then connection reliability improves, but area efficiency deteriorates
Solution Approach 1:
The patent merges the functions of charge transfer and electrical coupling into a single through-wiring line structure. This integrated approach eliminates the need for separate wiring components that would be required in conventional planar configurations, thereby maintaining connection reliability while significantly reducing the area required for wiring components on the second substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances area efficiency by directly coupling the charge accumulation section and the pixel transistor, minimizing the area required for components on the second semiconductor layer and improving the overall performance of the imaging device.
Implementation Method 1
a first semiconductor layer including, for each pixel, a photoelectric conversion section and a charge accumulation section that accumulates signal charge generated in the photoelectric conversion section
Data Source
AI summary
An imaging device according to an embodiment of the present disclosure includes: a first semiconductor layer including, for each pixel, a photoelectric conversion section and a charge accumulation section that accumulates signal charge generated in the photoelectric conversion section; a second semiconductor layer stacked on the first semiconductor layer and having a first surface provided with a pixel transistor, in which the pixel transistor has a three-dimensional structure and reads the signal charge from the charge accumulation section; and a through-wiring line that directly couples the charge accumulation section and a gate electrode of the pixel transistor to each other.