3D Perpendicular Magnetic Tunnel Junction With Thin Film Transistor Array
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Solution Overview
Problem
Conventional methods for forming arrays of three-dimensional perpendicular magnetic tunnel junction (pMTJ) sensors in magnetic random access memory (MRAM) face challenges due to temperature limitations, leading to structural degradation and increased production costs.
Innovation Solution
A method involving the formation of arrays with alternating pMTJ sensors and ohmic contact layers in a vertical direction using simple alternating thin-film deposition at lower temperatures, allowing for efficient and cost-effective production of high-density bit/cell arrays by stacking pMTJ cells and forming parallel connections of pMTJs and thin film transistors in a single step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional high-temperature methods are used to form pMTJ sensor arrays, then manufacturing capability is improved, but thermal degradation and component diffusion occur leading to structural degradation
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processes to low-temperature alternating thin-film deposition. This parameter change enables manufacturing of pMTJ sensor arrays while avoiding thermal degradation and component diffusion, thus maintaining structural integrity. The low-temperature process forms alternating layers of pMTJ sensors and ohmic contact layers without the harmful thermal effects of conventional methods.
2Quantity of substance
If high-density stacking of pMTJ cells is implemented, then memory density is improved, but processing complexity and production costs increase
Solution Approach 1:
The patent merges the formation of multiple pMTJ sensor layers and ohmic contact layers into a single integrated structure through alternating thin-film deposition. This combining approach achieves high-density stacking of pMTJ cells while simplifying the manufacturing process, as all layers are formed simultaneously in one continuous process rather than through multiple separate fabrication steps.
Solution Approach 2:
The patent transitions from planar to vertical three-dimensional stacking of pMTJ sensors and ohmic contact layers. By utilizing the vertical dimension with alternating layers deposited in the vertical direction, the patent achieves high memory density without increasing lateral footprint, while the alternating structure simplifies processing compared to forming each layer separately.
3Productivity
If alternating thin-film deposition is used to form pMTJ sensors and ohmic contact layers, then processing time is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs continuous alternating thin-film deposition to form pMTJ sensor layers and ohmic contact layers in an uninterrupted sequence. This continuous process reduces processing time compared to batch methods, while the alternating nature of deposition ensures precise layer formation through controlled switching between different materials, maintaining manufacturing precision through process continuity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density MRAM arrays with reduced processing time and costs, while maintaining the integrity of pMTJ sensors by avoiding thermal degradation and component diffusion.
Implementation Method 1
simple alternating thin-film deposition
Implementation Method 2
the transistor being functional to selectively electrically connect the pillar structure with the sourceline
Implementation Method 3
Magnetic Random Access Memory (MRAM) is a non-volatile data memory technology that stores data using magnetoresistive cells
Data Source
AI summary
A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.