3D Power Delivery Die Stacking for Stable On-Package Power
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Solution Overview
Problem
Existing packaged integrated circuits face challenges in efficiently delivering stable power due to noise and voltage fluctuations, which can be mitigated by integrating power delivery devices close to the integrated circuit, but this increases the package size and footprint.
Innovation Solution
The solution involves stacking package-integrated power delivery devices using techniques such as hybrid bonding, micro-bumping, and through-silicon vias to create a three-dimensional power delivery device die stack, allowing for efficient power delivery while minimizing the package footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power delivery devices are integrated into the package close to the integrated circuit, then power delivery optimization and noise filtering are improved, but the package floorplan size increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by implementing through-silicon vias (TSVs) that extend conductors through the entire thickness of the substrate. This allows power delivery devices to be positioned close to the integrated circuit in the vertical dimension without increasing the horizontal footprint, resolving the contradiction between power delivery optimization and package size.
2Reliability
If multiple power delivery devices are integrated within the package, then power delivery optimization is improved, but the package floorplan size increases
Solution Approach 1:
The patent enables multiple power delivery devices to be stacked vertically using TSV technology, allowing numerous devices to occupy the same horizontal footprint by utilizing the vertical dimension. This multi-device integration achieves superior power delivery optimization without proportionally increasing the package floorplan area.
Solution Approach 2:
The patent implements a nested structure where power delivery devices are embedded within the substrate thickness through TSVs, with conductors passing through the entire substrate to connect power and ground pads on opposite surfaces. This nesting approach allows multiple devices to share the same horizontal space while maintaining electrical functionality.
3Reliability
If power delivery devices are placed close to the integrated circuit, then parasitic capacitance and inductance are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs through-silicon via technology to create vertical interconnects that pass through the entire substrate thickness, enabling close placement of power delivery devices to the integrated circuit while maintaining manufacturability through established TSV fabrication processes.
Data Source
AI summary
A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.