3D Power Gating Cell Layout for Scaled MOSFET Integration
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices deteriorates their operating characteristics, necessitating improved integration and electrical properties.
Innovation Solution
The semiconductor device incorporates a power gating cell with a power gate electrode surrounding channel patterns, global and local power lines, and separation patterns, along with vertically stacked active regions and wiring layers to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET size is scaled down to increase integration, then integration density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOSFET structures to three-dimensional vertically stacked MOSFETs. Multiple active regions are stacked in the vertical direction (third direction perpendicular to substrate), allowing integration density to increase while maintaining adequate channel dimensions for acceptable operating characteristics. The power gate electrode extends in the first direction parallel to substrate while surrounding channel patterns that connect source/drain patterns between lower and upper active regions.
Solution Approach 2:
The power gate electrode structure surrounds and encloses the channel patterns, creating a nested configuration where the gate is positioned between source/drain patterns. This nested arrangement provides enhanced control over the channel while maintaining compact spatial footprint, enabling improved integration without sacrificing device performance.
2Productivity
If power gating cell structure is added to control power supply, then operational efficiency improves, but device complexity increases
Solution Approach 1:
The power gate electrode serves multiple functions: it controls the power supply to the MOSFET, acts as a gate structure for channel modulation, and provides a pathway for power distribution between lower and upper active regions. The global power line and local power line configuration enables both broad power distribution and localized power control, achieving multi-functionality that improves operational efficiency without proportionally increasing complexity.
Solution Approach 2:
The power distribution network is segmented into global power lines for broad distribution and local power lines for targeted delivery to specific active regions. This segmentation allows flexible power management where different regions can be independently controlled, improving operational efficiency while maintaining manageable structural complexity through modular power delivery.
Data Source
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AI summary
An example semiconductor device includes a lower wiring layer including lower wiring lines, an upper wiring layer including upper wiring lines, and a power gating cell between the lower and upper wiring layers. The power gating cell includes a first active region on a substrate and including first and second lower source/drain patterns and a first channel pattern connecting the first and second lower source/drain patterns with each other, a second active region on the first active region and including first and second upper source/drain patterns, and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to a top surface of the substrate. The lower wiring layer includes a global power line connected with the first lower source/drain pattern and a local power line connected with the second lower source/drain pattern.