3D Power Grid Layout Around Signal Pads to Reduce IR Drop
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Solution Overview
Problem
Current semiconductor devices face challenges in further reducing size and improving operating characteristics, particularly in 3D integrated circuits, due to increased power consumption and resistance issues in traditional power grid designs, which lead to higher IR drops and larger form factors.
Innovation Solution
The implementation of a 3D integrated circuit structure with offset power grid metal traces and bond pad metallization, where power grid metal traces are arranged in series of stripes with holes to minimize segmentation and reduce resistance, and hybrid bonding techniques to connect semiconductor devices, allowing for efficient power distribution and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional power grid designs are used in 3D integrated circuits, then device integration is achieved, but power consumption increases and IR drops increase
Solution Approach 1:
The patent transitions from traditional 2D power grid layouts to a 3D stacked architecture where power grid lines extend vertically through multiple semiconductor layers. This dimensional change allows power distribution across stacked dies, reducing horizontal current paths and associated IR drops while maintaining high integration density.
Solution Approach 2:
The power grid is segmented into multiple vertical sections distributed across different semiconductor layers. Each layer contains discrete power grid line segments that connect through vertical vias, distributing the power distribution function across multiple segments rather than relying on long horizontal traces in a single layer.
2Productivity
If traditional power grid designs are used in 3D integrated circuits, then device integration is achieved, but form factor increases
Solution Approach 1:
The patent utilizes the vertical dimension to accommodate power grid infrastructure, allowing power distribution networks to extend through the z-axis across stacked semiconductor dies. This removes the need for expanded horizontal area to accommodate traditional mesh-like power grids, maintaining compact form factor while achieving high integration density.
Solution Approach 2:
The power grid structure is nested within the vertical stack of semiconductor layers. Power grid lines in each layer are integrated within the same physical footprint as the active devices, with vertical connections nesting through multiple layers, effectively hiding the power distribution infrastructure within the device stack rather than requiring additional horizontal space.
3Ease of operation
If power grid lines are segmented to accommodate bond pads, then signal transmission is enabled, but resistance increases and IR drops increase
Solution Approach 1:
The patent resolves the conflict between signal transmission needs and power distribution efficiency by moving power grid continuity into the vertical dimension. Horizontal power grid lines in each layer remain continuous and are not segmented by bond pad locations, while vertical power connections through vias provide the necessary inter-layer signal and power transmission pathways.
Solution Approach 2:
Vertical vias serve as intermediary connectors that transmit both power and signals between layers without requiring horizontal segmentation of power grid lines. These via structures mediate the connection between bond pads in different layers while maintaining continuous power distribution paths within each layer, separating the signal transmission function from the power distribution function.
Data Source
AI summary
Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.