3D Power Module Structure for Lower Inductance and Warpage
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Solution Overview
Problem
The increase in power density of semiconductor devices leads to longer current paths, increased layout area, and higher parasitic inductance, affecting device performance and reliability due to the need for parallel chip connections.
Innovation Solution
A power module structure comprising an insulating substrate with separated conductive layers, a thermal interface material layer, and conductive adhesion layers, along with chips connected to these layers, is designed to reduce overall thickness and parasitic inductance, using an insulating metal substrate on a DBC ceramic substrate to minimize thermal resistance and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If semiconductor devices are combined in a package structure to improve power density, then output power increases in a small package, but the current path becomes longer and parasitic inductance increases
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where chips are arranged vertically on different conductive layers. This dimensional change allows current paths to be shortened by utilizing vertical connections through the substrate, thereby reducing parasitic inductance while maintaining high power density in a compact package.
Solution Approach 2:
The patent divides the package into multiple independent conductive layers (first conductive layer, second conductive layer, third conductive layer) with chips selectively placed on different layers. This segmentation allows independent optimization of current paths for each chip, enabling parallel current flow through multiple layers and reducing overall parasitic inductance.
2Power
If chips are connected in parallel to increase current handling capability, then power increases, but the layout area greatly increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking chips on multiple conductive layers within the substrate. This allows parallel connection of chips for increased current handling capability without expanding the planar layout area, as chips are arranged in the thickness direction rather than spreading out horizontally.
Solution Approach 2:
The patent embeds multiple chips and conductive layers within a compact three-dimensional package structure. Chips are nested on different layers, with each layer containing conductive patterns and chips that are vertically stacked, maximizing space utilization and enabling high power density without increasing layout area.
3Reliability
If multiple conductive layers are used to reduce parasitic inductance, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent forms the first conductive layer, second conductive layer, and third conductive layer sequentially during the manufacturing process, with each layer prepared in advance before chip placement. This preliminary formation of conductive structures simplifies the overall manufacturing by establishing the multi-layer architecture before chip assembly, reducing the complexity of integrating multiple layers later.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces overall thickness, thermal resistance, and parasitic inductance, enhancing device performance and reliability by minimizing warpage and avoiding multiple reflow processes for the chips.
Implementation Method 1
a first thermal interface material layer and a third conductive layer are formed in sequence on the first conductive layer
Implementation Method 2
The thermal conductive layer is disposed on the second surface
Data Source
AI summary
Provided are a power module and a manufacturing method thereof. The power module includes an insulating substrate, a first, a second and a third conductive layers, a first thermal interface material layer, a first and a second chips and a thermal conductive layer. The insulating substrate has a first and a second surfaces opposite to each other. The first and the second conductive layers are disposed on the first surface, and electrically separated from each other. The first thermal interface material layer is disposed on the first conductive layer. The third conductive layer is disposed on the first thermal interface material layer. The first chip is disposed on the third conductive layer and electrically connected to the third conductive layer. The second chip is disposed on the second conductive layer and electrically connected to the second conductive layer. The thermal conductive layer is disposed on the second surface.