3D Power Module Package Layout for Shorter Power Routing
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Solution Overview
Problem
Conventional semiconductor device packages experience significant power loss and IR drop due to long power routing paths, leading to reduced overall efficiency and increased thermal burden, especially in high-performance computing applications like CPUs, GPUs, or TPUs, necessitating more voltage regulator modules and higher material costs.
Innovation Solution
A semiconductor device package design featuring a substrate with a computing unit and a power module where the semiconductor die, power element, and passive element are vertically arranged, with the passive element, such as an inductor, assembled between the semiconductor die and the power element, reducing the power routing path and enhancing thermal conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional lateral power delivery system is used, then the power routing path is long, but this results in large power loss and large IR drop
Solution Approach 1:
The patent transitions from a conventional lateral (2D) power delivery architecture to a vertical (3D) stacked architecture. The power module is positioned directly above the computing unit on the same substrate, creating a vertical power routing path. This dimensional change dramatically shortens the current path length, reducing both power loss and IR drop while maintaining electrical connection integrity.
2Reliability
If the power routing path is long, then more voltage regulator modules are necessary, but this increases the bill of material cost
Solution Approach 1:
The patent integrates the power module and computing unit into a single stacked package on one substrate, merging functions that were previously separated across multiple components and substrates. This consolidation eliminates the need for additional voltage regulator modules by providing efficient power delivery through the vertical architecture, thereby reducing bill of material cost while maintaining reliability.
3Productivity
If the current consumption is increased, then the power efficiency should be improved, but the thermal burden increases
Solution Approach 1:
The passive element is positioned between the computing unit and power module, serving as an intermediary component. This element provides noise filtering and electrical isolation while the vertical architecture enables efficient thermal pathways. The stacked configuration allows heat to be conducted vertically through the substrate, managing thermal burden even at increased current consumption levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces power loss and IR drop, improving overall efficiency by decreasing equivalent series resistance (ESR) and equivalent series inductance (ESL) by 66% and 42.8%, respectively, and increasing power efficiency by 2% to 5.5%, while also facilitating better noise filtering and heat dissipation.
Implementation Method 1
The passive element, such as an inductor, assembled between the semiconductor die and the power element... decreasing equivalent series inductance (ESL) by 42.8%
Implementation Method 2
Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other... enhancing thermal conduction... facilitating better noise filtering and heat dissipation
Data Source
AI summary
A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.