3D Power Vias and Traces for Low-Resistance IC Package Delivery
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Solution Overview
Problem
High-performance integrated circuit (IC) dies face power bottlenecks due to lateral, vertical, and contact resistances in package-level conductor architectures, which are costly and complex to address with traditional methods such as increasing conductor widths and sizes or electroplating processes.
Innovation Solution
The use of high-throughput additive manufacturing (HTAM) via cold-spray deposition to create three-dimensionally structured low-resistance power conductors, including thick hybrid power traces and large power vias, and three-dimensional power pin contact pads with recessed surfaces and conductive malleable layers, significantly reducing resistance and contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional electroplating processes are used to create thick power conductors, then power resistance is reduced, but fabrication time and cost increase significantly
Solution Approach 1:
The patent replaces the electrochemical electroplating process with a mechanical deposition process (cold spray or high-velocity oxygen fuel deposition). This mechanical approach deposits metal particles onto the substrate to form thick power conductors without requiring lengthy electroplating cycles, thereby reducing fabrication time while achieving the necessary conductor thickness to minimize power resistance
Solution Approach 2:
The patent changes the deposition parameters from electrochemical (electroplating) to mechanical/thermal (cold spray or HVOF). By altering the fundamental deposition mechanism and controlling parameters such as particle velocity, temperature, and deposition rate, the process achieves thick conductor formation in significantly reduced time compared to traditional electroplating
2Reliability
If conductor width and thickness are increased to reduce lateral and vertical resistances, then power delivery performance improves, but fabrication complexity and cost increase
Solution Approach 1:
The patent applies different material compositions and structures to different regions of the power conductor system. Power traces and via fills use thick deposited metal layers for low resistance, while signal traces maintain standard thickness. This localized differentiation optimizes power delivery without unnecessarily complicating the fabrication of non-power features
Solution Approach 2:
The patent transitions from planar two-dimensional conductor traces to three-dimensional thick-film conductors by depositing metal particles that build up vertical height. This adds a third dimension (thickness) to the conductor geometry, enabling low-resistance power paths without requiring increased lateral dimensions that would consume valuable package area
3Reliability
If contact area between socket pins and land grid array pads is increased, then contact resistance is reduced, but package area is consumed
Solution Approach 1:
The patent creates highly conductive, thick metal deposits specifically at the contact pad regions where socket pins make contact. By concentrating the thick-film deposition technique at these critical contact points rather than uniformly across the entire package, the patent reduces contact resistance locally without consuming excessive package area
Solution Approach 2:
The patent creates composite contact structures combining the deposited thick-film metal layer with the underlying substrate material. This composite structure provides both low contact resistance through the thick conductive layer and mechanical support through the substrate, achieving low contact resistance without proportionally increasing contact pad area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables substantial reductions in power resistance and contact resistance, allowing for higher current carrying capacity with reduced fabrication complexity and cost, while maintaining or improving package dimensions and layer counts.
Implementation Method 1
high-throughput additive manufacturing (HTAM) via cold-spray deposition to create three-dimensionally structured low-resistance power conductors
Implementation Method 2
high-throughput additive manufacturing (HTAM) via cold-spray deposition to create three-dimensionally structured low-resistance power conductors
Data Source
AI summary
An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.