3D Power-Wall Layout for Vertically Stacked Transistor Tiers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device fabrication is to transition from two-dimensional (2D) circuits to three-dimensional (3D) scaling, which requires innovative methods to distribute power efficiently across vertically stacked transistors.
Innovation Solution
The proposed solution involves the creation of power-wall structures that support monolithically integrated 3D logic or memory devices, allowing power to be drawn at all levels throughout a device stack. This is achieved by forming power walls in a step-wise manner at each vertical device tier, enabling simultaneous formation of local interconnects and power wall sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D circuit layout is used, then manufacturing process is simple, but transistor density per unit area is limited
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertically stacked circuits by forming multiple transistor tiers stacked above each other. Power walls are formed as vertical structures extending through multiple tiers, enabling power distribution in the vertical dimension. This dimensional transition dramatically increases transistor density per unit area while managing the complexity through systematic 3D architecture design.
Solution Approach 2:
The power distribution network is segmented into multiple power walls, each serving specific transistor tiers. The power walls are formed in discrete sections corresponding to different vertical levels, with each segment connected to appropriate transistor tiers through local interconnects. This segmentation allows independent optimization and simplifies the manufacturing process for each tier.
2Use of energy by moving object
If power is delivered only from top down, then power distribution network is simple, but power distribution efficiency to lower tiers is poor
Solution Approach 1:
The power distribution network is divided into multiple power walls extending vertically through different transistor tiers. Each power wall segment is formed to serve specific tiers, with connections made through local interconnects at each level. This segmentation enables efficient power delivery to both upper and lower tiers without relying solely on top-down distribution.
Solution Approach 2:
Power distribution transitions from a single-plane 2D network to a 3D vertical architecture where power walls extend through multiple tiers. This allows power to be delivered laterally to transistor tiers at different vertical levels, dramatically improving power distribution efficiency to lower tiers while maintaining manageable complexity through systematic 3D design.
3Ease of manufacture
If power walls are formed after all transistor tiers, then manufacturing process is simple, but integration with local interconnects is difficult
Solution Approach 1:
The power wall formation process is segmented into discrete steps corresponding to each transistor tier. Power wall segments are formed sequentially as each tier is completed, with each segment aligned to its corresponding tier's local interconnects. This approach maintains manufacturing simplicity while achieving precise alignment through step-wise formation rather than requiring complex post-fabrication integration.
Solution Approach 2:
Power wall segments are formed in advance during the fabrication process of each corresponding transistor tier, rather than forming all power walls after all tiers are complete. This preliminary action ensures proper alignment with local interconnects from the outset, eliminating difficult post-fabrication alignment operations while maintaining process simplicity.
Data Source
AI summary
A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.