3D-Printed Conductive Wires for Package Substrate Interconnects

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Solution Overview

Problem

The existing semiconductor package manufacturing methods are complex, material-intensive, and environmentally impactful due to the need for multiple processes like thinning, drilling, and electroplating to create conductive vias for connecting circuit layers, limiting design flexibility and increasing production time and cost.

Innovation Solution

A package substrate is created using a 3D printing technique, where a carrier with multiple surfaces supports patterned conductive layers and 3D-printing conductive wires, allowing direct connection between layers without the need for vias, enabling flexible design and reduced material consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional via processes (thinning, drilling, rubbing, depositing, electroplating, filling) are used to connect conductive layers, then electrical connection between layers is achieved, but manufacturing complexity increases and material consumption increases

Engineering Contradiction:
Improveelectrical connection between layersVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the complex via formation processes (thinning, drilling, rubbing, depositing, electroplating, filling) from the manufacturing flow. Instead of using traditional via techniques to create conductive pathways through the substrate, the invention directly forms conductive wires on the substrate surface that connect different conductive layers, thereby removing multiple manufacturing steps while maintaining electrical connectivity functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the conventional approach by not creating holes or vias through the substrate to connect layers, but rather forming conductive wires on the substrate surface that bridge between layers. This reversal of the connection methodology eliminates the need for substrate penetration and associated complex processes, simplifying the manufacturing workflow while achieving the same electrical interconnection goal.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If traditional via processes are used to connect conductive layers, then electrical connection is achieved, but production time and cost increase

Engineering Contradiction:
Improveelectrical connection between layersVSAvoidproduction time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent removes the time-consuming via formation steps (thinning, drilling, rubbing, depositing, electroplating, filling) from the production sequence. By directly forming conductive wires on the substrate surface to connect layers, the invention eliminates multiple sequential operations, thereby significantly reducing total production time while maintaining reliable electrical connectivity between conductive layers.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If wire frame is restricted by single-layer structure, then manufacturing is simplified, but design flexibility of circuit is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidcircuit design flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent transitions from a single-layer wire frame structure to a multi-layer conductive structure with conductive wires formed on the substrate surface connecting different layers. This dimensional expansion from 2D single-layer to 3D multi-layer architecture enables complex circuit designs and enhanced adaptability while maintaining manufacturing feasibility through direct wire formation techniques.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the conductive structure into multiple independent layers with conductive wires connecting them, rather than using a single continuous layer. This segmentation allows each layer to be independently designed and optimized for specific circuit functions, greatly enhancing design flexibility and adaptability while keeping the manufacturing process manageable through sequential wire formation.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process, reduces material usage, and lowers production time and costs while enhancing design flexibility for semiconductor packages by enabling direct 3D printing of conductive wires on complex surfaces, thus improving the efficiency and environmental sustainability of the manufacturing method.

Implementation Method 1

the 3D-printing technique features in being capable of printing on a 3D surface, the 3D-printing conductive wire can be printed on the third surface of the carrier by the 3D-printing method

Methodology Applied
Scientific Effect3D Printing: 3D Printing

Data Source

PatentUS10096567B2Package substrate and package
Publication Date: 2018.10.09 WINBOND ELECTRONICS CORP
  • US10096567B2 patent drawing
  • US10096567B2 patent drawing
  • US10096567B2 patent drawing

AI summary

A package substrate including a carrier, a first patterned conductive layer, a second patterned conductive layer and a 3D-printing conductive wire is provided. The carrier has a first surface, a second surface and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface. The second patterned conductive layer is disposed on the second surface. The 3D-printing conductive wire is disposed on the third surface and connected between the first patterned conductive layer and the second patterned conductive layer.