3D-Printed Interconnect Substrate for Custom Semiconductor Packaging
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Solution Overview
Problem
The semiconductor packaging industry faces high costs due to complex interconnection processes, and existing facilities struggle to produce customized semiconductor chips for diverse applications such as IT, AI, vehicles, and smart factories.
Innovation Solution
The use of 3D printing technology for customized semiconductor packaging allows for the simplification of interconnection processes, reduction of costs, and creation of substrates with specific shapes and interconnection structures, thereby optimizing process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnection processes are used in semiconductor packaging, then electrical connection between semiconductor parts is achieved, but manufacturing costs increase sharply due to complex processes and structures
Solution Approach 1:
The patent changes the geometric parameters of interconnection structures by introducing curved paths instead of straight lines, and varying cross-sectional areas along the interconnection length. This allows optimization of electrical connection properties while reducing material usage and process complexity, thereby lowering manufacturing costs
Solution Approach 2:
The patent applies curvature to interconnection structures, using arc-shaped paths rather than straight lines. This curved geometry reduces stress concentration, improves current distribution, and enables more efficient routing that reduces the number of interconnection layers needed, thus simplifying the overall manufacturing process
2Productivity
If conventional semiconductor production facilities are used, then standard semiconductor chips are produced, but customization for diverse applications (AI, vehicles, smart factories) is difficult
Solution Approach 1:
The patent introduces dynamic adjustability in interconnection structures, allowing the geometry, length, and routing to be customized for different application requirements. This dynamic design enables the same production facility to efficiently produce varied customized chips for different markets without sacrificing productivity
Solution Approach 2:
The patent segments the interconnection design into modular units that can be independently configured and optimized for specific applications. This segmentation allows flexible combination of interconnection elements to create customized packaging solutions while maintaining efficient production through standardized modular components
3Reliability
If interconnection structures with various patterns are created to improve chip performance, then electrical connection distance and number increase, but device complexity increases sharply
Solution Approach 1:
The patent designs universal interconnection elements that can serve multiple functions: providing electrical connection, managing thermal stress, enabling signal routing, and facilitating mechanical alignment. This multi-functionality reduces the need for separate specialized structures, thereby reducing overall device complexity while maintaining or improving chip performance
Data Source
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AI summary
A material for a substrate for electrical connection between electronic components: a first composition comprising: an oligomer comprising a monomer represented by the following Chemical Formula 1; compound comprising at least two acrylate functional groups; and a photoinitiator; or a cured product of the first composition; wherein the R1 to the R4 are the same or different from each other, and are each independently a substituted or unsubstituted C1 to C40 alkyl group, wherein the Ar1 and the Ar2 are the same or different from each other, and are each independently a substituent containing a (meth)acrylate functional group, n1 is an integer of 1 to 50.