3D Processor Die Partitioning for High-Density Memory-Logic Computing
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Solution Overview
Problem
Conventional processors face inefficiencies due to limited computational density and complexity, inability to handle non-arithmetic functions, and difficulties in processing large data sets, particularly in applications like mathematical computing, computer simulation, configurable gate arrays, pattern processing, and neural networks, due to the limitations of two-dimensional integration and von Neumann architecture.
Innovation Solution
A discrete 3-D processor is designed with 2-D and 3-D circuits partitioned into separate dice, allowing for optimized manufacturing and performance of peripheral circuits and logic circuits, utilizing a 3D-M array and logic circuit in separate dice connected by inter-die connections, enabling more efficient computation and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional integration is used for processor design, then manufacturing simplicity is maintained, but computational density and complexity are limited
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional integration by stacking multiple functional layers vertically. The processor includes a first substrate with logic circuits, a second substrate with memory circuits, and a third substrate with peripheral circuits, all connected through vertical interconnect structures. This dimensional change enables significantly higher computational density while maintaining manufacturing feasibility through modular layering.
Solution Approach 2:
The processor is segmented into distinct functional substrates: logic circuits on a first substrate, memory circuits on a second substrate, and peripheral circuits on a third substrate. Each substrate can be manufactured and optimized independently, then integrated through vertical connections. This segmentation allows parallel development of different functional components and simplifies the manufacturing process for each layer.
2Productivity
If von Neumann architecture is used, then processor and memory are physically separated for simplicity, but data transfer bandwidth is limited
Solution Approach 1:
The patent merges the processor and memory into a single integrated three-dimensional structure where logic circuits and memory circuits are vertically stacked and directly connected. This eliminates the need for external system buses and enables high-bandwidth data transfer through short vertical interconnects, achieving both high productivity and unified architecture.
3Quantity of substance
If logic circuit and memory circuit are disposed on the same plane, then manufacturing is simplified, but internal memory capacity is limited
Solution Approach 1:
The patent places memory circuits on a separate substrate stacked vertically above the logic circuit substrate. This vertical arrangement in the third dimension allows significantly larger memory capacity without increasing the planar footprint, enabling high-capacity internal memory while maintaining compact form factor and manageable complexity.
4Productivity
If processor fetches data from external memory, then memory capacity can be large, but data transfer efficiency decreases
Solution Approach 1:
The patent integrates memory circuits directly onto the processor substrate stack, creating a unified processing-memory system. This eliminates external memory interfaces and system bus dependencies, enabling high-speed data access through direct vertical connections between logic and memory circuits, thereby achieving both high transfer efficiency and manageable integration complexity.
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, which comprise 3-D structures; whereas, the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the memory arrays, which comprise standard BEOL structures.