3D Processor Die Stacking for Memory-Logic Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional processors face inefficiencies in data transfer bandwidth due to the separation of processor and memory, limited computational density and complexity, and inability to efficiently implement non-arithmetic functions, particularly in applications like mathematical computing, computer simulation, configurable gate arrays, pattern processing, and neural networks.
Innovation Solution
A discrete 3-D processor is designed with 2-D and 3-D circuits partitioned into separate dice, allowing for optimized manufacturing and performance of peripheral and logic circuits, enabling efficient computation using memory-based operations and supporting a wider range of functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If processor and memory are physically separated in von Neumann architecture, then processor can perform logic operations, but data transfer bandwidth is limited due to distance and narrow system bus
Solution Approach 1:
The patent merges processor logic circuits and memory circuits onto the same semiconductor substrate, eliminating the physical separation between processor and memory. This integration allows logic circuits to directly access memory circuits through on-chip interconnects, dramatically increasing data transfer bandwidth while maintaining computational capability.
2Ease of manufacture
If logic circuit and memory circuit are disposed on the same plane (2-D integration), then manufacturing is simplified, but computational density is limited due to area constraints
Solution Approach 1:
The patent transitions from two-dimensional (2-D) integration to three-dimensional (3-D) integration by stacking multiple semiconductor substrates vertically. Logic circuits are disposed on a first semiconductor substrate while memory circuits are disposed on a second semiconductor substrate positioned above the first substrate, enabling significantly higher computational density without complicating the manufacturing process.
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The total-thickness difference of the BEOL layers between the memory arrays and the off-die peripheral-circuit components is substantially larger than the total-thickness difference of the BEOL layers between the non-memory circuits and the off-die peripheral-circuit components.