3D Storage-Processing Processor Layout for Memory Bandwidth Limits
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Solution Overview
Problem
Conventional processors, based on two-dimensional integration and von Neumann architecture, face inefficiencies in mathematical computing, computer simulation, pattern processing, and neural networks due to limited internal memory, narrow system bus bandwidth, and inability to directly implement non-arithmetic functions, leading to reduced computational density and complexity.
Innovation Solution
A discrete 3-D processor design that de-integrates 2-D and 3-D circuits, partitioning them into separate dice for optimized performance, featuring a plurality of storage-processing units with 3D-M arrays and processing circuits, allowing for increased array efficiency, better performance, and flexibility in functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2-D integration is used with von Neumann architecture, then device complexity is reduced and ease of manufacture is improved, but computational density and data transfer efficiency deteriorate
Solution Approach 1:
The patent transitions from conventional 2-D planar integration to 3-D vertical integration by stacking multiple processing layers and memory layers above the substrate. This dimensional change enables significantly higher computational density by utilizing the third dimension (vertical space) rather than only the horizontal plane, allowing multiple processing elements and memory structures to be stacked in a compact vertical arrangement.
Solution Approach 2:
The processor is segmented into multiple independent functional layers including substrate circuit layer, first memory layer, processing layer, and second memory layer. Each layer can be independently designed, manufactured, and optimized. This segmentation allows parallel processing operations across multiple layers simultaneously, thereby increasing overall computational density while maintaining manageable device complexity through modular architecture.
2Quantity of substance
If internal memory capacity is increased in conventional processors, then computational density improves, but the amount of internal memory available is limited by 2-D integration constraints
Solution Approach 1:
The patent implements 3-D vertical stacking of memory layers above the substrate, transitioning from 2-D planar memory expansion to 3-D vertical memory expansion. This allows internal memory capacity to be increased dramatically by utilizing vertical space rather than consuming additional horizontal die area, effectively decoupling memory capacity from die area constraints.
Solution Approach 2:
Multiple memory layers are nested vertically above each other in a stacked configuration, with first memory layer positioned above substrate circuit layer and second memory layer positioned above first memory layer. This nesting arrangement enables large total memory capacity to be achieved within a compact vertical footprint, significantly increasing internal memory capacity without proportionally increasing die area.
3Productivity
If processor and external memory are separated in von Neumann architecture, then device complexity is reduced, but data transfer bandwidth is limited
Solution Approach 1:
The patent merges processing circuits and memory structures into a unified 3-D integrated architecture where processing layer and memory layers are vertically stacked and closely coupled. This merging eliminates the separation between processor and memory inherent in von Neumann architecture, enabling direct high-bandwidth data transfer between processing elements and memory structures through short vertical interconnects, thereby dramatically increasing data transfer bandwidth.
Solution Approach 2:
The patent introduces substrate circuit layer as an intermediary between the stacked memory layers and processing layer, providing high-speed interconnect pathways. This intermediary layer with its dedicated interconnect structures serves as a high-bandwidth communication medium between memory and processing elements, overcoming the bandwidth limitations of conventional external memory interfaces.
4Productivity
If 3-D circuits are integrated with 2-D circuits on the same die, then manufacturing is simplified, but array efficiency deteriorates
Solution Approach 1:
The patent segments the integrated circuit into distinct 2-D substrate circuit layer and 3-D stacked memory layers, with each layer optimized for its specific function. The substrate circuit layer maintains 2-D planar geometry for ease of manufacturing, while the stacked memory layers utilize 3-D vertical geometry for high density. This segmentation allows each layer to be manufactured using appropriate processes while achieving high overall array efficiency through vertical integration.
Solution Approach 2:
Different regions and layers of the device are assigned different structural qualities: the substrate circuit layer maintains 2-D planar structure for manufacturing ease, while the memory layers above adopt 3-D vertical stacking for high array efficiency. This local differentiation of structural quality allows each region to be optimized for its specific requirements while maintaining overall manufacturing feasibility.
Data Source
AI summary
A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.