3D Processor Die Partitioning for Memory-Logic Bandwidth
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Solution Overview
Problem
Conventional processors based on two-dimensional integration face limitations in computational density, computational complexity, and efficiency due to the separation of processor and memory, leading to slow performance in mathematical computing, computer simulation, pattern processing, and neural networks, especially when dealing with large data sets.
Innovation Solution
A discrete 3-D processor is designed with 2-D and 3-D circuits partitioned into separate dice, allowing for optimized manufacturing and performance of logic and memory components, enabling efficient computation of non-arithmetic functions and models through memory-based computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If processor and memory are physically separated based on von Neumann architecture, then device complexity is reduced and ease of manufacture is improved, but data transfer bandwidth is limited and computational efficiency deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked architecture, where logic circuits and memory are vertically integrated across multiple layers. This dimensional change enables significantly increased bandwidth through multiple simultaneous data paths while maintaining manufacturing feasibility through advanced packaging technologies.
Solution Approach 2:
The patent merges previously separated processor and memory components into a unified three-dimensional integrated structure. Logic circuits and memory arrays are closely coupled across different layers, enabling data to remain stationary during processing and eliminating the bandwidth limitations of external memory interfaces.
2Device complexity
If logic circuit and memory circuit are disposed on the same plane, then device complexity is reduced, but computational density is limited
Solution Approach 1:
The patent utilizes three-dimensional stacking to increase computational density without proportionally increasing footprint area. Multiple logic layers and memory layers are vertically arranged, enabling thousands of processing elements to be packed into a compact volume while maintaining manageable interconnect complexity through hierarchical organization.
Solution Approach 2:
The patent implements a nested hierarchical structure where processing elements are organized in repeating units across multiple layers. Each layer contains nested arrays of processing elements that can be independently configured, allowing high computational density while maintaining modular complexity management.
3Ease of manufacture
If processor contains limited internal memory, then ease of manufacture is improved, but data transfer bandwidth to external memory is limited
Solution Approach 1:
The patent combines large容量的memory arrays directly with logic circuits in a three-dimensional stacked architecture. Memory is integrated within the same package and physically adjacent to processing elements, enabling bandwidths measured in terabytes per second through multiple simultaneous data paths between logic and memory layers.
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The total-number difference of the BEOL layers between the memory arrays and the off-die peripheral-circuit components is substantially larger than the total-number difference of the BEOL layers between the non-memory circuits and the off-die peripheral-circuit components.